{"title":"Hcompare: a hierarchical netlist comparison program","authors":"Pradeep Batra, David Cooke","doi":"10.1109/DAC.1992.227789","DOIUrl":null,"url":null,"abstract":"The authors present Hcompare, a hierarchical comparison tool. This tool does a true hierarchical comparison with the user-defined hierarchies. Errors are reported hierarchically in terms of user-defined blocks. Error reports are easy to read as errors are reported in terms of mismatched connections to design blocks. Run time is on the order of minutes even for large blocks with 2-3 million devices. Input to the tool is in the form of two netlists: one from the definition, typically schematic, and one from implementation, typically layout. The program has been used to compare layout vs schematic netlists for two chips with over two million devices each.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1992.227789","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The authors present Hcompare, a hierarchical comparison tool. This tool does a true hierarchical comparison with the user-defined hierarchies. Errors are reported hierarchically in terms of user-defined blocks. Error reports are easy to read as errors are reported in terms of mismatched connections to design blocks. Run time is on the order of minutes even for large blocks with 2-3 million devices. Input to the tool is in the form of two netlists: one from the definition, typically schematic, and one from implementation, typically layout. The program has been used to compare layout vs schematic netlists for two chips with over two million devices each.<>