Net partitions yield better module partitions

Abstract

The authors demonstrate that the dual intersection graph of the netlist strongly captures circuit properties relevant to partitioning. The main contribution of the analysis highlights advantages to using the dual representation of the logic design, and confirming that net structure and interrelationships, rather than module adjacencies, should constitute the primary descriptors of a circuit. In particular, the dual intersection graph representation of the netlist hypergraph yields much more natural circuit partitioning formulations, since it inherently emphasizes relationships between signal nets. The intersection graph yields a sparser circuit representation than traditional net models. An efficient algorithm, called IG-Match, is proposed for completing the net partition. The IG-Match method yielded significant performance improvements over previous ratio-cut partitioning methods.<>