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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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Optimization of primitive gate networks using multiple output two-level minimization 基于多输出两级最小化的原始门网络优化
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227761
A. A. Malik
{"title":"Optimization of primitive gate networks using multiple output two-level minimization","authors":"A. A. Malik","doi":"10.1109/DAC.1992.227761","DOIUrl":"https://doi.org/10.1109/DAC.1992.227761","url":null,"abstract":"A novel method for the optimization of a primitive gate network is presented. The author explains why a primitive gate representation may be necessary in certain situations and describes the problems associated with using two-level minimization in that case. He then describes a method for applying two-level minimization for the optimization of a primitive gate network. The approach is based on multiple-output two-level minimization as in MIS. It was effective in reducing the number of gates and connections in a network while maintaining the primitive gate representation.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123938855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Circuit enhancement by eliminating long false paths 通过消除长假路径增强电路
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227827
Hsi-Chuan Chen, D. Du, Siu-Wing Cheng
{"title":"Circuit enhancement by eliminating long false paths","authors":"Hsi-Chuan Chen, D. Du, Siu-Wing Cheng","doi":"10.1109/DAC.1992.227827","DOIUrl":"https://doi.org/10.1109/DAC.1992.227827","url":null,"abstract":"The authors propose to identify and perform logic replacement for a portion; called a segment, of a long path instead of the path itself. This results in less gate and lead duplication and hence reduction in the increase of circuit area. They give sufficient conditions for the choice of segments that can maintain the performance of the circuit. If the restriction on the choice of segments is relaxed then two very effective heuristics are obtained for removing long false paths. The experimental results show that the proposed algorithm and heuristics are feasible for large designs and the increase in circuit area is significantly reduced.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126637736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A near optimal algorithm for technology mapping minimizing area under delay constraints 时延约束下最小面积技术映射的近最优算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227753
K. Chaudhary, Massoud Pedram
{"title":"A near optimal algorithm for technology mapping minimizing area under delay constraints","authors":"K. Chaudhary, Massoud Pedram","doi":"10.1109/DAC.1992.227753","DOIUrl":"https://doi.org/10.1109/DAC.1992.227753","url":null,"abstract":"The authors examine the problem of mapping a Boolean network using gates from a finite size cell library to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. The approach consists of two steps: In the first step, delay functions are computed at all nodes in the network, and in the second step the mapping solution is generated based on the computed delay functions and the required times at the primary outputs. For a NAND-decomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying all delay constraints if such a solution exists. The algorithm has polynomial run time on a node-balanced tree and is easily extended to mapping a directed acyclic graph. The results compared favorably with those of the MIS2.2 mapper.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
The Electronic Design Interchange Format EDIF: present and future 电子设计交换格式EDIF:现在与未来
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227802
H. J. Kahn, R. Goldman
{"title":"The Electronic Design Interchange Format EDIF: present and future","authors":"H. J. Kahn, R. Goldman","doi":"10.1109/DAC.1992.227802","DOIUrl":"https://doi.org/10.1109/DAC.1992.227802","url":null,"abstract":"The authors review the present status and current developments of the Electronic Design Interchange Format, EDIF. EDIF is now the primary mechanism for transfer of connectivity and schematic data. However, real practical problems exist and are being tackled. Some of the difficulties that have arisen are reviewed and some solutions are discussed. Some of the new ideas being developed for inclusion in the new release of EDIF (Version 2 1 0) are introduced.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131108541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
APT: an area-performance-testability driven placement algorithm APT:区域性能可测试性驱动的放置算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227846
Sungho Kim, P. Banerjee, V. Chickermane, J. Patel
{"title":"APT: an area-performance-testability driven placement algorithm","authors":"Sungho Kim, P. Banerjee, V. Chickermane, J. Patel","doi":"10.1109/DAC.1992.227846","DOIUrl":"https://doi.org/10.1109/DAC.1992.227846","url":null,"abstract":"The authors present a placement algorithm that uses the notion of partial scan and that addresses testability as well as performance. The cost of including a flip-flop cell in a scan path is obtained in the placement process and guides the selection of scan flip-flops. This is then followed by a cell resizing step in which logic cells change their widths and timing characteristics using the templates provided by a cell library. This reduces delays in the critical timing paths and delays caused by inserting scan flip-flops. Experimental results on the ISCAS benchmark show that combining the performance and testability optimizations in the placement level resulted in better solutions in terms of area, timing, and fault coverage.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133735244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new efficient approach to multilayer channel routing problem 多层信道路由问题的一种新的有效方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227819
S. Fang, Wu-Shiung Feng, Shian-Lang Lee
{"title":"A new efficient approach to multilayer channel routing problem","authors":"S. Fang, Wu-Shiung Feng, Shian-Lang Lee","doi":"10.1109/DAC.1992.227819","DOIUrl":"https://doi.org/10.1109/DAC.1992.227819","url":null,"abstract":"A very efficient multilayer channel router, the M/sup 3/CR, is described. The goal of M/sup 3/CR is to use an optimum number of tracks for any multilayer routing instance in the dogleg-free routing model. M/sup 3/CR has a simple time complexity because it is not a maze-running-based router. The experiment demonstrated that M/sup 3/CR produced an optimum number of tracks for all the test examples from 4 through 8 layers in a very short time. The variable-wire-width consideration based on the design rules is discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133821770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A pin permutation algorithm for improving over-the-cell channel routing 一种用于改进蜂窝上信道路由的引脚排列算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227816
C.Y.R. Chen, C. Y. Hou
{"title":"A pin permutation algorithm for improving over-the-cell channel routing","authors":"C.Y.R. Chen, C. Y. Hou","doi":"10.1109/DAC.1992.227816","DOIUrl":"https://doi.org/10.1109/DAC.1992.227816","url":null,"abstract":"A dynamic-programming-based algorithm is presented to determine proper gate and terminal positions such that, when over-the-cell routers are used, the area above and below the channel can be utilized more effectively and the channel density can be greatly reduced. The problem formulation and previous work are discussed. The terminology and notation are introduced. A polynomial-time algorithm is presented. Experimental results showed that the proposed algorithm considerably reduces the channel density.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114365913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
High level synthesis of pipelined instruction set processors and back-end compilers 流水线指令集处理器和后端编译器的高级综合
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227847
Ing-Jer Huang, A. Despain
{"title":"High level synthesis of pipelined instruction set processors and back-end compilers","authors":"Ing-Jer Huang, A. Despain","doi":"10.1109/DAC.1992.227847","DOIUrl":"https://doi.org/10.1109/DAC.1992.227847","url":null,"abstract":"The authors propose a synthesis methodology for high-performance pipelined instruction set processors. Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of the Advanced Design Automation System (ADAS) which controls the hardware-software interactions at the micro-architecture level. The key function of Piper is to perform pipeline scheduling with any fixed instruction-latency, and generate a reorder table for a back-end compiler to resolve potential pipeline hazards existing in the design. Models for performance and cost of both hardware and software are developed to characterize the design space. A synthesis example of a simple instruction set processor illustrates Piper's synthesis capabilities and how the performance and cost of hardware and software are estimated.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116059148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Over-the-cell routers for new cell model 蜂窝路由器的新蜂窝模型
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227814
Bo Wu, N. Sherwani, N. D. Holmes, M. Sarrafzadeh
{"title":"Over-the-cell routers for new cell model","authors":"Bo Wu, N. Sherwani, N. D. Holmes, M. Sarrafzadeh","doi":"10.1109/DAC.1992.227814","DOIUrl":"https://doi.org/10.1109/DAC.1992.227814","url":null,"abstract":"The authors present new over-the-cell routing techniques for the standard cell design style. They have developed both a two-layer and a three-layer router. The key feature of the routers is the use of a new cell model, in which the terminals are located in the middle of the cells in the second metal layer. This model is similar to one currently being developed for three-layer cell libraries in industry. Both the routers were implemented in C on a SUN SPARCstation 1+ and tested with several benchmarks including PRIMARY 1 and PRIMARY II from MCNC. Both of the routers outperformed all existing routers. In addition, both ICR-2 and ICR-3 were very fast-for example, ICR-3 completed the routing of the entire PRIMARY I benchmark in 5.8 s.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114066120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
CAD Framework Initiative-a user perspective CAD框架倡议-用户视角
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227801
Todd J. Scallan
{"title":"CAD Framework Initiative-a user perspective","authors":"Todd J. Scallan","doi":"10.1109/DAC.1992.227801","DOIUrl":"https://doi.org/10.1109/DAC.1992.227801","url":null,"abstract":"The author presents an overview of the CAD Framework Initiative (CFI) from a user's perspective. CFI is an industry consortium whose charter is to define interface standards that facilitate integration of design automation tools and design data for the benefit of end users and vendors worldwide. Integration problems faced by CAD users are introduced, followed by a discussion of the concept of a CAD framework. CFI's role in the evolution toward framework standardization is described. Specifically highlighted are key demonstrations of CFI's progress that have been conducted at the Design Automation Conference. End user benefits and expectations with respect to CFI are discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122872956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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