A near optimal algorithm for technology mapping minimizing area under delay constraints

The authors examine the problem of mapping a Boolean network using gates from a finite size cell library to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. The approach consists of two steps: In the first step, delay functions are computed at all nodes in the network, and in the second step the mapping solution is generated based on the computed delay functions and the required times at the primary outputs. For a NAND-decomposed tree, subject to load calculation errors, this two step approach finds the minimum area mapping satisfying all delay constraints if such a solution exists. The algorithm has polynomial run time on a node-balanced tree and is easily extended to mapping a directed acyclic graph. The results compared favorably with those of the MIS2.2 mapper.<>