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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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Exact evaluation of diagnostic test resolution 诊断测试分辨率的准确评估
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227780
K. Kubiak, Steven Parkes, W. Fuchs, R. Saleh
{"title":"Exact evaluation of diagnostic test resolution","authors":"K. Kubiak, Steven Parkes, W. Fuchs, R. Saleh","doi":"10.1109/DAC.1992.227780","DOIUrl":"https://doi.org/10.1109/DAC.1992.227780","url":null,"abstract":"The authors introduce a new measure of the diagnostic resolution of a test set: the sizes of all equivalence classes in the circuit under the test set. This measure is a better indicator of the diagnostic capabilities of a test set than single-value metrics based on undistinguished pairs of faults or completely distinguished faults. A symbolic algorithm for computing equivalence class sizes has been used to evaluate the diagnostic resolution of deterministic single-stuck-at fault test sets for ISCAS combinational and sequential benchmark circuits.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
AWEsymbolic: compiled analysis of linear(ized) circuits using asymptotic waveform evaluation 编译分析线性(化)电路使用渐近波形评估
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227834
John Y. Lee, R. Rohrer
{"title":"AWEsymbolic: compiled analysis of linear(ized) circuits using asymptotic waveform evaluation","authors":"John Y. Lee, R. Rohrer","doi":"10.1109/DAC.1992.227834","DOIUrl":"https://doi.org/10.1109/DAC.1992.227834","url":null,"abstract":"Asymptotic Waveform Evaluation (AWE) is shown to be effective in the symbolic analysis of linear(ized) circuits. AWEsymbolic efficiently and accurately produces reduced order models of both frequency and time domain behavior of linear(ized) circuits. By use of moment level partitioning, the numeric and symbolic computations are substantially decoupled, hence increasing computation speed. Results for AWEsymbolic showed a marked decrease in execution time as compared to a full AWE analysis, while producing identical results. The use of AWEsymbolic in the frequency domain and in the time domain is illustrated.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Performance-driven system partitioning on multi-chip modules 多芯片模块上的性能驱动系统分区
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227862
M. Shih, E. Kuh, R. Tsay
{"title":"Performance-driven system partitioning on multi-chip modules","authors":"M. Shih, E. Kuh, R. Tsay","doi":"10.1109/DAC.1992.227862","DOIUrl":"https://doi.org/10.1109/DAC.1992.227862","url":null,"abstract":"The authors propose an efficient algorithm for system partitioning under timing and capacity constraints. They consider the problem of assigning functional blocks into slots on multi-chip modules during high level design to have fast feedback on the impact of high level design decisions. A clustering step is used to ensure timing correctness, followed by packaging and the K&L algorithm to satisfy capacity constraints while minimizing net crossings. The method is unique in that net crossings are minimized while satisfying timing and capacity constraints. Test results showed that the method eliminated timing violations and obtained a comparable number of net crossings to that of the K&L algorithm using similar CPU time. The method can be extended to use partitioning algorithms other than K&L.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129427972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Over-the-cell channel routing for high performance circuits 用于高性能电路的蜂窝通道路由
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227815
Sivakumaran Natarajan, N. Sherwani, N. D. Holmes, M. Sarrafzadeh
{"title":"Over-the-cell channel routing for high performance circuits","authors":"Sivakumaran Natarajan, N. Sherwani, N. D. Holmes, M. Sarrafzadeh","doi":"10.1109/DAC.1992.227815","DOIUrl":"https://doi.org/10.1109/DAC.1992.227815","url":null,"abstract":"The authors present a new three-layer over-the-cell channel routing algorithm, WILMA3 (wire length minimization algorithm 3), for high-performance circuits. This router not only minimizes the channel height by OTC routing but also minimizes the net lengths. They have also developed a two-layer router, WILMA2. Both WILMA2 and WILMA3 achieve reduction in channel height while maintaining the net length greater than its length in the two-layer channel routing. Experimental results with WILMA2 indicated that WILMA2 can produce routings that are comparable to existing two-layer over-the-cell routers. Both WILMA2 and WILMA3 achieved these results, while maintaining the net length bound.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128752388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Specification partitioning for system design 对系统设计进行规范划分
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227833
F. Vahid, D. Gajski
{"title":"Specification partitioning for system design","authors":"F. Vahid, D. Gajski","doi":"10.1109/DAC.1992.227833","DOIUrl":"https://doi.org/10.1109/DAC.1992.227833","url":null,"abstract":"The authors focus on the goal of partitioning a behavior to satisfy chip-capacity constraints while considering system-performance constraints. A hardware implementation is assumed with a uniform chip technology. A new approach is introduced which partitions entire computations of a behavioral specification, such as processes and procedures, into chip behavioral specifications. The usefulness of the approach was demonstrated. The results of partitioning several examples using the specification partitioning tool being developed are provided.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132408195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 119
Fuzzy logic approach to placement problem 定位问题的模糊逻辑方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.5555/113938.119626
Rung-Bin Lin, E. Shragowitz
{"title":"Fuzzy logic approach to placement problem","authors":"Rung-Bin Lin, E. Shragowitz","doi":"10.5555/113938.119626","DOIUrl":"https://doi.org/10.5555/113938.119626","url":null,"abstract":"The authors apply fuzzy reasoning to the placement of sea-of-gate arrays. Fuzzy logic is used to optimize a process of decision making in physical design. Multiple objectives such as utilization of area, routability, and timing were considered simultaneously and balanced by fuzzy logic algorithms. The experiments demonstrated that solutions obtained by fuzzy logic were of much better quality than those achieved by standard techniques.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133739496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
At-speed delay testing of synchronous sequential circuits 同步顺序电路的高速延迟测试
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227840
I. Pomeranz, S. Reddy
{"title":"At-speed delay testing of synchronous sequential circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/DAC.1992.227840","DOIUrl":"https://doi.org/10.1109/DAC.1992.227840","url":null,"abstract":"Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Test-set preserving logic transformations 保持逻辑转换的测试集
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227760
Michael J. Batek, J. Hayes
{"title":"Test-set preserving logic transformations","authors":"Michael J. Batek, J. Hayes","doi":"10.1109/DAC.1992.227760","DOIUrl":"https://doi.org/10.1109/DAC.1992.227760","url":null,"abstract":"Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead designs, thus verifying some recent simulation results.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133343634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Efficient sum-to-one subsets algorithm for logic optimization 逻辑优化的高效和一子集算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227762
Kuang-Chien Chen, M. Fujita
{"title":"Efficient sum-to-one subsets algorithm for logic optimization","authors":"Kuang-Chien Chen, M. Fujita","doi":"10.1109/DAC.1992.227762","DOIUrl":"https://doi.org/10.1109/DAC.1992.227762","url":null,"abstract":"An optimization algorithm, RENO, was proposed by K.C. Chen et al. (1991), in which a given network was minimized by optimally resynthesizing each gate in the network. It is shown that the resynthesis problem in RENO can be transformed into a minimum-cost sum-to-one subset problem based on a given cost function, which is an important problem that often occurs in logic optimization algorithms. Efficient procedures for solving both sum-to-one subsets and minimum-cost sum-to-one subset problems are presented and applied to multilevel network optimization algorithms. Both the efficiency and quality of these algorithms are greatly improved. The application of these techniques to multinode minimization using Boolean relations is also discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132323898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Inductive verification of iterative systems 迭代系统的归纳验证
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227809
June-Kyung Rho, F. Somenzi
{"title":"Inductive verification of iterative systems","authors":"June-Kyung Rho, F. Somenzi","doi":"10.1109/DAC.1992.227809","DOIUrl":"https://doi.org/10.1109/DAC.1992.227809","url":null,"abstract":"Recent advances in binary decision diagram (BDD)-based algorithms have brought much larger circuits than before within the reach of verification programs. The authors show how inductive proof procedures can derive information on regular circuits in optimal time, e.g. they can perform reachability analysis in linear time or check the equivalence of two iterative circuits in time independent of the length of the two arrays. The algorithms presented rely on the canonicity of BDDs to make the inductive steps efficient. The authors have experimented with the techniques described and compared them with the conventional techniques on a few examples.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121370204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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