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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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A new hierarchical layout compactor using simplified graph models 一种基于简化图模型的分层布局压缩器
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227785
Wonjong Kim, J. Lee, Hyunchul Shin
{"title":"A new hierarchical layout compactor using simplified graph models","authors":"Wonjong Kim, J. Lee, Hyunchul Shin","doi":"10.1109/DAC.1992.227785","DOIUrl":"https://doi.org/10.1109/DAC.1992.227785","url":null,"abstract":"A new hierarchy-preserving hierarchical compactor which can be used with either 1-D or 2-D leafcell compaction techniques has been developed. The compactor is applicable to hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after compaction. A hierarchical compactor based on the suggested simplified graph model has been developed and experimental results on several benchmark examples showed that the proposed method was satisfactory.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121410475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Transformation-based high-level synthesis of fault-tolerant ASICs 基于转换的高级容错集成电路综合
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227803
R. Karri, A. Orailoglu
{"title":"Transformation-based high-level synthesis of fault-tolerant ASICs","authors":"R. Karri, A. Orailoglu","doi":"10.1109/DAC.1992.227803","DOIUrl":"https://doi.org/10.1109/DAC.1992.227803","url":null,"abstract":"The authors present a transformation-based approach to the high-level synthesis of fault-tolerant application-specific ICs (ASICs) satisfying a given performance constraint but requiring less than proportional increase in hardware over their nonredundant counterparts. They propose a synthesis methodology to exploit hardware minimizing transformations. A simple set of transformations are identified that minimize the fault-tolerance overhead. The selected transformations make the final design resilient to common mode failures. These transformations can be composed to form a rich set of complex transformations. An algorithm is presented to automatically identify structures in a flow graph where transformations can improve hardware utilization, and transformations that suit the structure best are applied. The system has been used to schedule several flow graphs.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129321710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Design process management for CAD frameworks CAD框架的设计过程管理
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227752
M. Jacome, S. W. Director
{"title":"Design process management for CAD frameworks","authors":"M. Jacome, S. W. Director","doi":"10.1109/DAC.1992.227752","DOIUrl":"https://doi.org/10.1109/DAC.1992.227752","url":null,"abstract":"The authors introduce a new mechanism for planning and managing the VLSI design process. The design process manager significantly enhances the capabilities of CAD frameworks, relieving designers from dealing with low-level details, thereby allowing them to concentrate on the more innovative aspects of design. A model for representing design processes is described. To demonstrate the suitability of the design process model, a prototype design process manager, called Minerva, has been developed. Minerva is described.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing 性能驱动布局和FPGA路由的迭代和自适应松弛分配
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227746
J. Frankle
{"title":"Iterative and adaptive slack allocation for performance-driven layout and FPGA routing","authors":"J. Frankle","doi":"10.1109/DAC.1992.227746","DOIUrl":"https://doi.org/10.1109/DAC.1992.227746","url":null,"abstract":"The authors gives a generalization, called the limit-bumping algorithm (LBA), of a procedure of H. Youssef et al. (1990) that transforms initial connection delays into upper limits on delay suitable for performance-driven layout. LBA is a simple way to distribute slacks using arbitrary allocation functions. It is shown that lower and upper bounds on connection delays can be used in the computation of upper limits for initial layout and for layout improvement. The methods have been integrated into a delay-sensitive router for field programmable gate arrays (FPGAs). In 22 standard benchmark designs, feasible system clock periods were reduced in every case by an average of 14% and as much as 32%.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"11 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114127032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 98
Representing conditional branches for high-level synthesis applications 表示高级合成应用程序的条件分支
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227853
Minjoong Rim, R. Jain
{"title":"Representing conditional branches for high-level synthesis applications","authors":"Minjoong Rim, R. Jain","doi":"10.1109/DAC.1992.227853","DOIUrl":"https://doi.org/10.1109/DAC.1992.227853","url":null,"abstract":"The authors outline a new representation of behavioral specification for high-level synthesis applications. The main features of the representation are correct handling of conditional branches; the ability to tradeoff between control-select and data-select forms; keeping minimum necessary precedence relationships; correct representation of all conditional actions; and simplified mutual exclusion testing and correct determination of bit-widths and value transfers. The representation is simple and can be easily generated automatically.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114146960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
On the stability of moment-matching approximations in asymptotic waveform evaluation 渐近波形估计中矩匹配近似的稳定性
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227835
D. Anastasakis, N. Gopal, Seok-Yoon Kim, L. Pileggi
{"title":"On the stability of moment-matching approximations in asymptotic waveform evaluation","authors":"D. Anastasakis, N. Gopal, Seok-Yoon Kim, L. Pileggi","doi":"10.1109/DAC.1992.227835","DOIUrl":"https://doi.org/10.1109/DAC.1992.227835","url":null,"abstract":"Asymptotic waveform evaluation (AWE), which is based upon moment-matching, has been demonstrated as an efficient approach for CAD circuit simulation/analysis. The authors describe an approach for overcoming the inherent instability associated with AWE and moment-matching methods as they apply to circuit analysis problems. The efficiency and accuracy of this algorithm were demonstrated in the analysis of large, lumped RLC interconnect-circuit analysis problems and printed circuit board interconnections.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115175981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Computing optimal clock schedules 计算最佳时钟调度
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227771
T. G. Szymanski
{"title":"Computing optimal clock schedules","authors":"T. G. Szymanski","doi":"10.1109/DAC.1992.227771","DOIUrl":"https://doi.org/10.1109/DAC.1992.227771","url":null,"abstract":"The author considers the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates that recently proposed linear programming (LP) approaches to this problem require excessive computation time. An alternative method is proposed in which LP constraints are generated selectively, thus allowing fast solution. Various formulations of short path constraints are discussed, as are experimental results for large circuits.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115759234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
SWiTEST: a switch level test generation system for CMOS combinational circuits 用于CMOS组合电路的开关电平测试生成系统
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227868
Kuen-Jong Lee, C. Njinda, M. Breuer
{"title":"SWiTEST: a switch level test generation system for CMOS combinational circuits","authors":"Kuen-Jong Lee, C. Njinda, M. Breuer","doi":"10.1109/DAC.1992.227868","DOIUrl":"https://doi.org/10.1109/DAC.1992.227868","url":null,"abstract":"The authors present a switch level test generation system called SWiTEST. SWiTEST deals with bridging, breaking, stuck-open/on and stuck-at-faults. It employs both logic and current monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework for SWiTEST is based on the PODEM algorithm. Some experimental results are presented and discussed. The experimental results imply that switch level test generation can be done in CPU time that is within an order of magnitude of that required for gate level test generation.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114379707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Area and delay mapping for table-look-up based field programmable gate arrays 基于表查找的现场可编程门阵列的区域和延迟映射
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227776
Prashant S. Sawkar, D. E. Thomas
{"title":"Area and delay mapping for table-look-up based field programmable gate arrays","authors":"Prashant S. Sawkar, D. E. Thomas","doi":"10.1109/DAC.1992.227776","DOIUrl":"https://doi.org/10.1109/DAC.1992.227776","url":null,"abstract":"The authors present a new approach to technology mapping for area and delay for truth-table-based field programmable gate arrays. They view the area and delay optimizations during technology mapping as a case of clique partitioning for which an efficient heuristic was developed. Alternate decompositions were explored by using Shannon expansion. Experimental results are included that were obtained by this approach for area and delay optimization on a number of benchmark examples.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128183070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Plane parallel A* maze router and its application to FPGAs 平面并行A*迷宫路由器及其在fpga中的应用
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227797
M. Palczewski
{"title":"Plane parallel A* maze router and its application to FPGAs","authors":"M. Palczewski","doi":"10.1109/DAC.1992.227797","DOIUrl":"https://doi.org/10.1109/DAC.1992.227797","url":null,"abstract":"A plane-parallel maze-routing method for field programmable gate arrays is presented. It was demonstrated that a plane-parallel approach was significantly faster than traditional approaches, without compromising quality as measured by routing length. A framework is established for unified code to support traditional wire routing, timing driven routing, and plane parallel and global routing.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
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