Computing optimal clock schedules

Abstract

The author considers the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates that recently proposed linear programming (LP) approaches to this problem require excessive computation time. An alternative method is proposed in which LP constraints are generated selectively, thus allowing fast solution. Various formulations of short path constraints are discussed, as are experimental results for large circuits.<>