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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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Process independent constraint graph compaction 处理独立约束图压缩
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227786
D. G. Boyer
{"title":"Process independent constraint graph compaction","authors":"D. G. Boyer","doi":"10.1109/DAC.1992.227786","DOIUrl":"https://doi.org/10.1109/DAC.1992.227786","url":null,"abstract":"The author describes the DASL symbolic layout system, which is used to create experimental VLSI circuits. The DASL constraint graph compactor requires no user intervention to produce a process-independent design. It also produces results that are electrically correct, e.g., that control the placement of substrate contacts. In other constraint graph compaction if there is nothing to constrain an element's placement, it will slide as far to the left as possible. A technique has been developed that controls the size of the tubs and the placement of the substrate contacts. A given design can be recompacted for a new process, therefore without any user intervention being necessary. The substrate contact sliding problem is constrained by minimizing the area of the tubs in the unique fashion that is discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124835736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Estimation of average switching activity in combinational and sequential circuits 组合和顺序电路中平均开关活度的估计
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227826
Abhijit Ghosh, S. Devadas, K. Keutzer, Jacob K. White
{"title":"Estimation of average switching activity in combinational and sequential circuits","authors":"Abhijit Ghosh, S. Devadas, K. Keutzer, Jacob K. White","doi":"10.1109/DAC.1992.227826","DOIUrl":"https://doi.org/10.1109/DAC.1992.227826","url":null,"abstract":"The authors address the problem of estimating the average power dissipated in VLSI combinational and sequential circuits, under random input sequences. Switching activity is strongly affected by gate delays and for this reason a general delay model is used in estimating switching activity. The method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals. In sequential circuits, the input sequence applied to the combinational portion of the circuit is highly correlated because some of the inputs to the combinational logic are flip-flop outputs representing the state of the circuit. Methods are presented to probabilistically estimate switching activity in sequential circuits. These methods automatically compute the switching rates and correlations between flip-flop outputs.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 549
FARM: an efficient feed-through pin assignment algorithm FARM:一种高效的馈通引脚分配算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227747
Xianlong Hong, Jin Huang, Chung-Kuan Cheng, E. Kuh
{"title":"FARM: an efficient feed-through pin assignment algorithm","authors":"Xianlong Hong, Jin Huang, Chung-Kuan Cheng, E. Kuh","doi":"10.1109/DAC.1992.227747","DOIUrl":"https://doi.org/10.1109/DAC.1992.227747","url":null,"abstract":"The authors propose an efficient feedthrough pin assignment algorithm, FARM, to minimize the maximum channel density, and at the same time to reduce the wire length and via number. A novel vertical channel routing formulation is devised to model the pin assignment problem. A multirow density minimization followed with a single-row pin assignment is proposed to complete the assignment process. Some experimental results and a comparison with previous work are given.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123272295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Zero skew clock net routing 零偏差时钟网路由
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227749
Ting-Hai Chao, Y. Hsu, Jan-Ming Ho
{"title":"Zero skew clock net routing","authors":"Ting-Hai Chao, Y. Hsu, Jan-Ming Ho","doi":"10.1109/DAC.1992.227749","DOIUrl":"https://doi.org/10.1109/DAC.1992.227749","url":null,"abstract":"The authors present an algorithm, called the zero skew segment tree method (ZSTM), for the clock net routing problem. To eliminate the lock skew and minimize the total wire length, ZSTM recursively partitions the sink nodes into two subsets which have equal loadings and minimum sum of diameters, and then constructs a zero skew segment tree according to the partitioning result. The final layout of the clock net can be decided by the channel information of the routing region. Experiments showed that ZSTM improved the wire length by 15% and the maximum delay by 3% over the published results. It also completely eliminated the clock skew.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"59 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 151
An integrated approach to realistic worst-case design optimization of MOS analog circuits MOS模拟电路现实最坏情况设计优化的集成方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227795
A. Dharchoudhury, S. Kang
{"title":"An integrated approach to realistic worst-case design optimization of MOS analog circuits","authors":"A. Dharchoudhury, S. Kang","doi":"10.1109/DAC.1992.227795","DOIUrl":"https://doi.org/10.1109/DAC.1992.227795","url":null,"abstract":"The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Synthesis from production-based specifications 从基于生产的规范中合成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227837
A. Seawright, F. Brewer
{"title":"Synthesis from production-based specifications","authors":"A. Seawright, F. Brewer","doi":"10.1109/DAC.1992.227837","DOIUrl":"https://doi.org/10.1109/DAC.1992.227837","url":null,"abstract":"The authors describe a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant machine is derived from a hierarchy of sub-machine descriptions, each represented by a production. The production-based specification (PBS) consists of productions annotated with HDL action code, and forms the input to a design tool which outputs procedural HDL tailored for hardware synthesis. Due to the concise nature of this form of specification, the technique can save enormous labor in the construction of procedural specifications for these machines. Novel aspects of this research include the compilation of a PBS with HDL action clauses into synthesizable procedural HDL and the approach to specification of machine behavior in the event of exceptional conditions.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134641511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Optimal scheduling and allocation of embedded VLSI chips 嵌入式VLSI芯片的优化调度与分配
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227851
C. Gebotys
{"title":"Optimal scheduling and allocation of embedded VLSI chips","authors":"C. Gebotys","doi":"10.1109/DAC.1992.227851","DOIUrl":"https://doi.org/10.1109/DAC.1992.227851","url":null,"abstract":"A new integer programming (IP) model is presented for synthesizing high speed embedded VLSI chips. A model is presented for simultaneous scheduling, selecting types of functional units, allocation and determining the clock period. Functional units can be chained, multicycled, or pipelined, with different speed and area characteristics. A large number of optimal architectures, satisfying area, speed, and interface constraints, can be synthesized. The synthesis problem is transformed into a tight IP model based on polyhedral theory. A branch and bound algorithm produces globally optimal architectures in practical CPU execution times. It is shown that by simultaneously selecting clock periods and chaining operations, the architectures, synthesized by the optimal architectural synthesis model, are up to 23% faster than previously published architectures. Up to 30 times improvement in CPU execution times is obtained.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Characterization of Boolean functions for rapid matching in EPGA technology mapping EPGA技术映射中快速匹配布尔函数的表征
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227775
Ulf Schlichtmann, F. Brglez, M. Hermann
{"title":"Characterization of Boolean functions for rapid matching in EPGA technology mapping","authors":"Ulf Schlichtmann, F. Brglez, M. Hermann","doi":"10.1109/DAC.1992.227775","DOIUrl":"https://doi.org/10.1109/DAC.1992.227775","url":null,"abstract":"The authors introduce characteristic signatures for Boolean functions. The signatures do not exhibit sensitivity to permutations of input variables. These signatures are used to develop a method of rapidly matching subcircuits with cells in a large library. The procedure is analogous to hashing. Filters are discussed that were found to be useful in improving the matching of variables before applying the equivalence verification. Experimental results and the figure of merit of various signatures are outlined.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133040886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A performance driven macro-cell placement algorithm 一种性能驱动的宏单元格放置算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227845
T. Gao, P. M. Vaidya, C. Liu
{"title":"A performance driven macro-cell placement algorithm","authors":"T. Gao, P. M. Vaidya, C. Liu","doi":"10.1109/DAC.1992.227845","DOIUrl":"https://doi.org/10.1109/DAC.1992.227845","url":null,"abstract":"The authors present a new performance driven macro-cell placement algorithm. Placement of modules is guided by a set of upper- and lower-bounds on the net wire lengths. A convex programming algorithm is used to compute a set of upper-bounds on the net wire lengths which will ensure that timing requirements between input and output signals are satisfied. A set of lower-bounds is also computed to control signal skews at intermediate points of the circuit. Artificial nets are introduced between all pairs of modules. Lower-bounds on the lengths of the artificial nets are computed to avoid module overlaps in the placement. A modified min-cut placement algorithm is then used to generate a placement that satisfies the upper- and lower-bounds. An iterative procedure is used to modify the set of upper- and lower-bounds to improve the quality of the placement result. Experimental results on eight test examples are included.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
On the temporal equivalence of sequential circuits 时序电路的时间等效性
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227770
Narendra V. Shenoy, K. J. Singh, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"On the temporal equivalence of sequential circuits","authors":"Narendra V. Shenoy, K. J. Singh, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/DAC.1992.227770","DOIUrl":"https://doi.org/10.1109/DAC.1992.227770","url":null,"abstract":"The authors extend the abstract notion of temporal behavior to compare arbitrary circuits with arbitrary multiphase clocking schemes. They consider the input-output behavior of circuits with respect to time. Properties are discussed that remain invariant under certain transformations. Constraints are derived that permit a legal retiming in the case of multiphase sequential circuits with edge triggered and/or transparent latches. For a particular design style an efficient procedure is described to check for temporal equivalence of sequential circuits. A model and a formal definition for the temporal behavior of an arbitrary multiphase circuits and an algorithm for formal verification of the temporal behavior of circuits are outlined.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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