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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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An improved synthesis algorithm for multiplexor-based PGAs 一种改进的多路PGAs合成算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227774
R. Murgai, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"An improved synthesis algorithm for multiplexor-based PGAs","authors":"R. Murgai, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/DAC.1992.227774","DOIUrl":"https://doi.org/10.1109/DAC.1992.227774","url":null,"abstract":"The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Recurrence equations and the optimization of synchronous logic circuits 递归方程与同步逻辑电路的优化
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227823
M. Damiani, G. Micheli
{"title":"Recurrence equations and the optimization of synchronous logic circuits","authors":"M. Damiani, G. Micheli","doi":"10.1109/DAC.1992.227823","DOIUrl":"https://doi.org/10.1109/DAC.1992.227823","url":null,"abstract":"The authors present a formulation for the problem of optimizing synchronous logic across register boundaries. They describe the degrees of freedom that are the don't-care conditions of an embedded subnetwork by means of sets of execution traces, described implicitly by synchronous recurrence equations. The optimization problem reduces to that of finding minimum-cost solutions to such equations. An exact solution algorithm for this problem is presented, along with approximations that improve its computational efficiency. The feasibility and effectiveness of the approach were demonstrated on synchronous benchmark circuits.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128221576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Superpipelined control and data path synthesis 超流水线控制和数据路径合成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227807
U. Prabhu, B. Pangrle
{"title":"Superpipelined control and data path synthesis","authors":"U. Prabhu, B. Pangrle","doi":"10.1109/DAC.1992.227807","DOIUrl":"https://doi.org/10.1109/DAC.1992.227807","url":null,"abstract":"The authors describe a superpipelined control and data path synthesis system. The system can handle pipelined modules in the data path, perform functional pipelining in the data path, and schedule the data path using a pipelined controller. Three control styles-serial, parallel, and pipelined-were implemented. The system automatically picks one depending on the data path, the clock frequency, and the functional unit and control path delays. The results showed that using a modifiable clock cycle time and a parameterized control style can significantly improve the throughput of high-performance systems.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116410248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Algorithms for current monitor based diagnosis of bridging and leakage faults 基于电流监测的桥接和漏电故障诊断算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227779
S. Chakravarty, Minsheng Liu
{"title":"Algorithms for current monitor based diagnosis of bridging and leakage faults","authors":"S. Chakravarty, Minsheng Liu","doi":"10.1109/DAC.1992.227779","DOIUrl":"https://doi.org/10.1109/DAC.1992.227779","url":null,"abstract":"Current monitor based diagnosis algorithms for bridging and leakage faults for combinational and sequential circuits are described. Experimental evaluation results of these algorithms are represented. The algorithms do not use fault dictionaries. A set of ordered-pairs of sets (SOPS) is used to represent all two line bridging faults. If m is the size of the circuit then SOPS uses O(m) space to represent these faults. The resulting algorithm takes time O(mN), where N is the size of the test set.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124769862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems 数字系统自动合成中的移动帧调度和混合调度分配
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227854
M. Nourani, C. Papachristou
{"title":"Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems","authors":"M. Nourani, C. Papachristou","doi":"10.1109/DAC.1992.227854","DOIUrl":"https://doi.org/10.1109/DAC.1992.227854","url":null,"abstract":"The authors present two algorithms for the scheduling and allocation phases in high-level synthesis under time and resource constraints. This is achieved by formulating these problems in terms of Lyapunov's stability theorem using a transformation technique between the design space and the dynamic system space. These algorithms are based on moves in the design space, which correspond to the moves towards the equilibrium point in the dynamic system space. The scheduling algorithm takes care of mutually exclusive operations, loop folding, multi-cycle operations, chained operations and pipelining. The mixed scheduling-allocation algorithm can handle all of these scheduling applications and simultaneously perform allocation of functional units, registers and interconnects while minimizing the overall cost.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125082649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
High-level synthesis with pin constraints for multiple-chip designs 多芯片设计中具有引脚约束的高级合成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227831
Y. Hung, A. C. Parker
{"title":"High-level synthesis with pin constraints for multiple-chip designs","authors":"Y. Hung, A. C. Parker","doi":"10.1109/DAC.1992.227831","DOIUrl":"https://doi.org/10.1109/DAC.1992.227831","url":null,"abstract":"The authors describe an approach to multi-chip data path synthesis, given a behavorial description which has already been partitioned into a number of clusters, with the feasibility of clusters determined. The problem is divided into interchip connection determination and scheduling. A heuristic search technique is described for interchip connection determination. A pipelined RTL design consisting of multiple chips was produced by the software. A set of communication buses among the chips was determined, and the values to be transferred were scheduled on the pins and buses. The RTL design produced satisfied user-supplied constraints, including the number of input-output pins on individual chips.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130156319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Functional approaches to generating orderings for efficient symbolic representations 为有效的符号表示生成排序的函数方法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227810
M. R. Mercer, R. Kapur, D. Ross
{"title":"Functional approaches to generating orderings for efficient symbolic representations","authors":"M. R. Mercer, R. Kapur, D. Ross","doi":"10.1109/DAC.1992.227810","DOIUrl":"https://doi.org/10.1109/DAC.1992.227810","url":null,"abstract":"The authors present a functional approach to generating orderings for representing functions. They develop a cost function which closely mimics the ordered binary decision diagram operations and can be quickly computed. Using the cost as a metric for an ordering, an annealing procedure was used to arrive at good variable orderings. The results obtained by simulated annealing are compared to orderings generated from heuristics that use circuit topology to arrive at a variable ordering.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130460729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Hierarchical test generation under intensive global functional constraints 密集全局功能约束下的分层测试生成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227825
Jaushin Lee, J. Patel
{"title":"Hierarchical test generation under intensive global functional constraints","authors":"Jaushin Lee, J. Patel","doi":"10.1109/DAC.1992.227825","DOIUrl":"https://doi.org/10.1109/DAC.1992.227825","url":null,"abstract":"The authors address the system-level functional constraint problem for hierarchical test generation. They propose several approaches to solve both control constraints and bus constraints. For control constraints, circuit behavior information is exploited to derive valid control Boolean covers for different modules. For bus constraints, a constant value bus constraint abstraction technique and a test cube justification technique are introduced. These proposed algorithms have been implemented in the hierarchical test generation package, ARTEST, and four high-level circuits with different constraint characteristics have been tested in experiments. The experimental results show the effectiveness of combining the control cover abstraction technique and the test cube justification technique as a complete solution to the global functional constraint problem.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121505544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Zero delay versus positive delay in an incremental switch-level simulator 增量开关级模拟器中的零延迟与正延迟
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227766
L. G. Jones
{"title":"Zero delay versus positive delay in an incremental switch-level simulator","authors":"L. G. Jones","doi":"10.1109/DAC.1992.227766","DOIUrl":"https://doi.org/10.1109/DAC.1992.227766","url":null,"abstract":"The author presents methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. In experiments run on switch-level versions of the ISCAS combinational and sequential benchmarks, incremental switch-level simulation with mixed zero/integer delay was four times faster on the average than incremental switch-level simulation with only positive integer delays.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117336742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transient simulation of lossy interconnect 有损互连的瞬态仿真
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227857
Shen Lin, E. Kuh
{"title":"Transient simulation of lossy interconnect","authors":"Shen Lin, E. Kuh","doi":"10.1109/DAC.1992.227857","DOIUrl":"https://doi.org/10.1109/DAC.1992.227857","url":null,"abstract":"A new approach for transient simulation of lossy transmission lines terminated in arbitrary nonlinear elements is presented. The approach is based on convolution simulation. By making use of the Pade approximations of each line's characteristic admittance function and exponential propagation function, the authors derive a recursive convolution formulation, which greatly reduces the computation used to perform convolutions. They analyze the errors introduced by Pade approximations and develop a scheme to determine the necessary order for an approximation. The approach was implemented in the stepwise equivalent conductance MOS timing simulator, SWEC, and, therefore, no Newton-Raphson iteration was needed to simulate lossy lines with nonlinear terminals. The simulation results of SWEC were compared with the results of SPICE3.e; SWEC, which gives accurate results, can be one to two orders-of-magnitude faster.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
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