An improved synthesis algorithm for multiplexor-based PGAs

R. Murgai, R. Brayton, A. Sangiovanni-Vincentelli
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引用次数: 54

Abstract

The authors address the problem of synthesis for a popular class of programmable gate array architectures, the multiplexer-based architectures. They present improved techniques for minimizing the number of basic blocks used to implement a combinational circuit. One source of improvement is the use of if-then-else DAGs (directed acyclic graphs) as subject graphs along with BDDs (binary decision diagrams). An important contribution is a very fast algorithm which always gives a match for a function onto the basic block of the architecture, when one exists. Results obtained on a number of benchmark examples are given.<>
一种改进的多路PGAs合成算法
作者解决了一类流行的可编程门阵列体系结构的综合问题,即基于多路器的体系结构。他们提出了改进的技术,以尽量减少用于实现组合电路的基本块的数量。改进的一个来源是使用if-then-else dag(有向无环图)和bdd(二元决策图)作为主题图。一个重要的贡献是一个非常快速的算法,当一个函数存在时,它总是在架构的基本块上给出一个匹配的函数。给出了在若干基准算例上得到的结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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