Zero delay versus positive delay in an incremental switch-level simulator

Abstract

The author presents methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. In experiments run on switch-level versions of the ISCAS combinational and sequential benchmarks, incremental switch-level simulation with mixed zero/integer delay was four times faster on the average than incremental switch-level simulation with only positive integer delays.<>