Recurrence equations and the optimization of synchronous logic circuits

Abstract

The authors present a formulation for the problem of optimizing synchronous logic across register boundaries. They describe the degrees of freedom that are the don't-care conditions of an embedded subnetwork by means of sets of execution traces, described implicitly by synchronous recurrence equations. The optimization problem reduces to that of finding minimum-cost solutions to such equations. An exact solution algorithm for this problem is presented, along with approximations that improve its computational efficiency. The feasibility and effectiveness of the approach were demonstrated on synchronous benchmark circuits.<>