LATTIS: an iterative speedup heuristic for mapped logic

Abstract

The author describes heuristic problems for performance optimization of mapped combinational logic, implemented in the system LATTIS (logic area-time tradeoff for integrated systems). LATTIS currently has six transform types: gate repowering, buffer insertion, downpowering of noncritical fanouts of the critical path, gate duplication, DeMorgan's laws, and timing-directed factorization and remapping of subcircuits. From among the transforms applicable on the critical path. LATTIS chooses the one with maximum benefit/cost. Cost is increase in area, and benefit is improvement in local slack, weighted by the number of primary input/outputs affected. The delay-area curves produced by LATTIS for the 70 largest circuits of the 1991 MCNC multilevel combinational logic benchmark set are given.<>