Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers

Abstract

The authors present a concurrent fault simulation algorithm. The pipelined algorithm is suitable for implementation on memory limited hardware accelerators and message passing multicomputers or specialized hardware. The architecture of the system and the data structures and algorithms for some of the crucial parts of the fault simulation algorithm are outlined. For pipelined architectures, fault simulation is illustrated for circuits modeled at mixed functional and gate levels. The results indicate an order of magnitude speed up compared to a production quality simulator running on a SUN SPARC2.<>