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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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BDDMAP: a technology mapper based on a new covering algorithm BDDMAP:基于新覆盖算法的技术映射器
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227755
David S. Kung, R. Damiano, T. A. Nix, David J. Geiger
{"title":"BDDMAP: a technology mapper based on a new covering algorithm","authors":"David S. Kung, R. Damiano, T. A. Nix, David J. Geiger","doi":"10.1109/DAC.1992.227755","DOIUrl":"https://doi.org/10.1109/DAC.1992.227755","url":null,"abstract":"The authors present a technology mapper, BDDMAP, which combines the strengths of rule-based heuristics and algorithmic techniques. Rule-based heuristics or functional matching is invoked to match the type of technology gates for which it is most efficient. The algorithmic part of BDDMAP lies in the covering process. The novel aspects of the covering algorithm are using an anticipative cost function, global cost propagation and handling of multiple output gates. The mapping problem is discussed in the context of matching of patterns and covering of the target network. The matching process is discussed followed by benchmark results.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128965846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Parallel waveform relaxation of circuits with global feedback loops 具有全局反馈回路的并行波形松弛电路
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227871
T. A. Johnson, A. Ruehli
{"title":"Parallel waveform relaxation of circuits with global feedback loops","authors":"T. A. Johnson, A. Ruehli","doi":"10.1109/DAC.1992.227871","DOIUrl":"https://doi.org/10.1109/DAC.1992.227871","url":null,"abstract":"Feedback loops often severely degrade the performance of waveform relaxation techniques in solving large circuit analysis problems. Several new approaches have been studied to provide greater parallelism and faster convergence for such circuits. WRV256, an experimental waveform-relaxation-based parallel circuit simulator for the Victor family of distributed memory parallel machines, was used to study performance tradeoffs of partitioning and scheduling algorithms for circuits containing global feedback loops. This investigation included circuits ranging from less than 300 to over 93000 transistors. Several of the circuits were extracted directly from a 16 Mb DRAM design.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An efficient algorithm for microword length minimization 一种有效的微字长度最小化算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227805
R. Puri, J. Gu
{"title":"An efficient algorithm for microword length minimization","authors":"R. Puri, J. Gu","doi":"10.1109/DAC.1992.227805","DOIUrl":"https://doi.org/10.1109/DAC.1992.227805","url":null,"abstract":"The problem of microword length minimization is crucial to the synthesis of microprogrammed controllers in digital systems. The authors formulate the problem as a graph partitioning problem. They employ a local search approach to further reduce the microword length. The algorithm is capable of finding fast and near-optimal solutions for very large size microcodes, efficiently. The algorithm was tested with practical microcodes and with large size examples generated from random graphs. The experimental results are compared with those of other methods.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Validating discrete event simulations using event pattern mappings 使用事件模式映射验证离散事件模拟
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227768
B. Gennart, D. Luckham
{"title":"Validating discrete event simulations using event pattern mappings","authors":"B. Gennart, D. Luckham","doi":"10.1109/DAC.1992.227768","DOIUrl":"https://doi.org/10.1109/DAC.1992.227768","url":null,"abstract":"The authors introduce a new concept for the validation of discrete event simulations, based on recursively detecting and naming patterns of events. In this methodology, simulation results are presented as a small set of easy-to-understand high-level events. This hierarchical presentation of simulation results greatly reduces the designer's work in browsing through simulation results and detecting errors. Language constructs are introduced for defining event patterns that are VAL+ mappings. A software tool based on mappings is described and results of using the debugger on three large examples are included.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130192339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks 高度可测试的固定极性和/异或规范网络的快速精确和准极小极小化
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227867
Andisheh Sarabi, M. Perkowski
{"title":"Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks","authors":"Andisheh Sarabi, M. Perkowski","doi":"10.1109/DAC.1992.227867","DOIUrl":"https://doi.org/10.1109/DAC.1992.227867","url":null,"abstract":"The authors introduce fast exact and quasi-minimal algorithms for minimal fixed polarity AND/XOR canonical representation of Boolean functions. The method uses features of arrays of disjoint cubes representations of functions to identify the minimal networks. These features can drastically reduce the search space and provide high quality heuristics for quasi-minimal representations. Experimental results show that these special AND/XOR networks, on the average, have a similar number of terms to Boolean AND/OR networks while there were functions for which AND/XOR circuits were much smaller. The circuits generated are much more testable.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129677591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
On the distribution of fault coverage and test length in random testing of combinational circuits 组合电路随机测试中故障覆盖和测试长度的分布
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227781
Amitava Majumdar, S. Sastry
{"title":"On the distribution of fault coverage and test length in random testing of combinational circuits","authors":"Amitava Majumdar, S. Sastry","doi":"10.1109/DAC.1992.227781","DOIUrl":"https://doi.org/10.1109/DAC.1992.227781","url":null,"abstract":"Models for the process of testing faults in combinational circuits under both random and pseudorandom tests are proposed. Based on these models, the probability distribution function (PDF) of fault coverage is derived. By using an important relationship between the PDF of fault coverage and that of test length, an expression is derived for the PDF of test length. These analytical results allow expressions to be obtained for expected values of fault coverage and test length, and other important statistics not obtained by existing techniques. Empirical results validating these models for fault coverage analysis are presented from experiments with several circuits. Techniques for estimation of necessary parameters, based on both statistical and probabilistic models, are proposed. These techniques, combined with the theoretical results, define a comprehensive methodology for random testability prediction of combinational circuits.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132099679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Tools to aid in wiring rule generation for high speed interconnects 帮助高速互连的布线规则生成的工具
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227758
P. Franzon, S. Simovich, M. Steer, M. Basel, S. Mehrotra, Tom Mills
{"title":"Tools to aid in wiring rule generation for high speed interconnects","authors":"P. Franzon, S. Simovich, M. Steer, M. Basel, S. Mehrotra, Tom Mills","doi":"10.1109/DAC.1992.227758","DOIUrl":"https://doi.org/10.1109/DAC.1992.227758","url":null,"abstract":"The MetaSim allows multiple simulation studies to be automatically specified, conducted, and analyzed in such a fashion so as to produce wiring rules for layout tools. The authors describe the operation of MetaSim and give an example of its use. One of MetaSim's current engines, Transim, is a convolution simulator that incorporates a robust, rapid, and accurate method for the simulation of coupled, lossy interconnect structures specified with frequency-dependent parameters. Transim solves the problem of incorporating transient circuit simulation with nonlinear devices, with transmission line simulation in the frequency domain.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129571082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Analyzing cycle stealing on synchronous circuits with level-sensitive latches 电平敏感锁存器同步电路的周期窃取分析
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227772
I. Lin, J. A. Ludwig, K. Eng
{"title":"Analyzing cycle stealing on synchronous circuits with level-sensitive latches","authors":"I. Lin, J. A. Ludwig, K. Eng","doi":"10.1109/DAC.1992.227772","DOIUrl":"https://doi.org/10.1109/DAC.1992.227772","url":null,"abstract":"The authors present a new method to fully explore cycle steal opportunities in the timing analysis for level-sensitive synchronous circuit designs. The algorithm first constructs a latch graph from a timing analysis on the combinational logic, and then it analyzes cycle stealing based on overlay timing relationships among latch nodes. A breadth-first search examines all possible cycle stealing among latches. The algorithm also considers the fact that cycle stealing is topology dependent. The timing analysis program also takes into account the variation of clock width and leading and training clock edges in each latch, so the data can be used to assist physical design. The program has been implemented on an IBM RISC System/6000 coupled with an IBM IC design system. The results showed the benefit of using cycle steal opportunities in the design.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123477503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
On efficient concurrent fault simulation for synchronous sequential circuits 同步顺序电路的高效并发故障仿真
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227784
Dong-Ho Lee, S. Reddy
{"title":"On efficient concurrent fault simulation for synchronous sequential circuits","authors":"Dong-Ho Lee, S. Reddy","doi":"10.1109/DAC.1992.227784","DOIUrl":"https://doi.org/10.1109/DAC.1992.227784","url":null,"abstract":"The authors report on an efficient fault simulation method for synchronous sequential circuits. The method is based on concurrent fault simulation and has the simplicity of deductive fault simulation. Several new ideas to reduce computation time and memory requirements are proposed. New fault simulators were developed to simulate transition faults as well as stuck-at faults. The experimental results demonstrate that the proposed method is effective for simulating faults in large synchronous sequential circuits in the workstation environment.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An engineering environment for hardware/software co-simulation 硬件/软件协同仿真的工程环境
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227848
D. Becker, Raj K. Singh, S. Tell
{"title":"An engineering environment for hardware/software co-simulation","authors":"D. Becker, Raj K. Singh, S. Tell","doi":"10.1109/DAC.1992.227848","DOIUrl":"https://doi.org/10.1109/DAC.1992.227848","url":null,"abstract":"The authors describe an environment supporting concurrent hardware and software engineering for high performance systems. In place of a conventional bread-boarded prototype, they used distributed communicating processes to allow software and simulated hardware to interact. The Cadence Verilog-XL simulator was extended to enable software debugging and testing using hardware simulation. The environment was proven during a successful system design.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125251843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
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