Analyzing cycle stealing on synchronous circuits with level-sensitive latches

Abstract

The authors present a new method to fully explore cycle steal opportunities in the timing analysis for level-sensitive synchronous circuit designs. The algorithm first constructs a latch graph from a timing analysis on the combinational logic, and then it analyzes cycle stealing based on overlay timing relationships among latch nodes. A breadth-first search examines all possible cycle stealing among latches. The algorithm also considers the fact that cycle stealing is topology dependent. The timing analysis program also takes into account the variation of clock width and leading and training clock edges in each latch, so the data can be used to assist physical design. The program has been implemented on an IBM RISC System/6000 coupled with an IBM IC design system. The results showed the benefit of using cycle steal opportunities in the design.<>