硬件/软件协同仿真的工程环境

D. Becker, Raj K. Singh, S. Tell
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引用次数: 87

摘要

作者描述了一个支持高性能系统并行硬件和软件工程的环境。代替传统的面包板原型,他们使用分布式通信过程来允许软件和模拟硬件交互。扩展了Cadence Verilog-XL模拟器,可以使用硬件模拟进行软件调试和测试。该环境在成功的系统设计中得到了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An engineering environment for hardware/software co-simulation
The authors describe an environment supporting concurrent hardware and software engineering for high performance systems. In place of a conventional bread-boarded prototype, they used distributed communicating processes to allow software and simulated hardware to interact. The Cadence Verilog-XL simulator was extended to enable software debugging and testing using hardware simulation. The environment was proven during a successful system design.<>
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