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[1992] Proceedings 29th ACM/IEEE Design Automation Conference最新文献

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The role of long and short paths in circuit performance optimization 长、短路径在电路性能优化中的作用
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227745
Siu-Wing Cheng, Hsi-Chuan Chen, D. Du, A. Lim
{"title":"The role of long and short paths in circuit performance optimization","authors":"Siu-Wing Cheng, Hsi-Chuan Chen, D. Du, A. Lim","doi":"10.1109/DAC.1992.227745","DOIUrl":"https://doi.org/10.1109/DAC.1992.227745","url":null,"abstract":"The authors consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To develop the timing of the circuit, they use a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physical level, the problem is that of applying transistor sizing and delay buffer insertion to achieve specified upper bounds on clock period and latency. Experimental results are presented that reflect the complexity of the optimization problem. The clock period determination can also be extended to circuits with feedbacks.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126023186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Hierarchical pitchmatching compaction using minimum design 使用最小设计的分层间距匹配压实
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227787
C. Bamji, R. Varadarajan
{"title":"Hierarchical pitchmatching compaction using minimum design","authors":"C. Bamji, R. Varadarajan","doi":"10.1109/DAC.1992.227787","DOIUrl":"https://doi.org/10.1109/DAC.1992.227787","url":null,"abstract":"A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input layout as well as the pitchmaking and abutment constraints between the cells. The hierarchical compactor automatically factors out the regularity in the layout and performs almost all of its operations on a minimum design. This novel and unique formulation of the hierarchical compaction problem enables compaction time to be a function of the irregularity rather than the size of the layout.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126010498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Time constrained allocation and assignment techniques for high throughput signal processing 高通量信号处理的时间约束分配和分配技术
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227849
W. Geurts, F. Catthoor, H. Man
{"title":"Time constrained allocation and assignment techniques for high throughput signal processing","authors":"W. Geurts, F. Catthoor, H. Man","doi":"10.1109/DAC.1992.227849","DOIUrl":"https://doi.org/10.1109/DAC.1992.227849","url":null,"abstract":"A technique for the allocation of complex application specific datapaths is presented. The technique is especially suited for the synthesis of application specific architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set of datapaths is allocated and the available cycle budget is automatically distributed over the different blocks of the hierarchy in one global optimization process. Results for a number of real life examples are presented.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128248261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Coalgebraic division for multilevel logic synthesis 多层逻辑综合的共代数除法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227763
W. Hsu, W. Shen
{"title":"Coalgebraic division for multilevel logic synthesis","authors":"W. Hsu, W. Shen","doi":"10.1109/DAC.1992.227763","DOIUrl":"https://doi.org/10.1109/DAC.1992.227763","url":null,"abstract":"By introducing two Boolean properties into an algebraic division operation, a subset of Boolean division can be performed with approximately the same complexity as the algebraic division implemented in the misII environment. The extended algebraic division algorithm is called coalgebraic division. The experimental results show that the execution time of coalgebraic division is very close to that of algebraic division. With a simple restriction during division, coalgebraic division can also preserve the network testability as well as the test patterns.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132031632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Delay fault test generation for scan/hold circuits using Boolean expressions 用布尔表达式生成扫描/保持电路的延迟故障测试
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227843
D. Bhattacharya, P. Agrawal, V. Agrawal
{"title":"Delay fault test generation for scan/hold circuits using Boolean expressions","authors":"D. Bhattacharya, P. Agrawal, V. Agrawal","doi":"10.1109/DAC.1992.227843","DOIUrl":"https://doi.org/10.1109/DAC.1992.227843","url":null,"abstract":"A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated for each fault. These constraints are then manipulated to obtain robust tests, if they exist; otherwise, nonrobust tests are obtained from the constraint functions, if they exist. An implementation of this technique was used to analyze delay fault testability of several ISCAS '89 benchmark circuits.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Delay fault models and test generation for random logic sequential circuits 随机逻辑顺序电路的延迟故障模型和测试生成
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227842
T. Chakraborty, V. Agrawal, M. Bushnell
{"title":"Delay fault models and test generation for random logic sequential circuits","authors":"T. Chakraborty, V. Agrawal, M. Bushnell","doi":"10.1109/DAC.1992.227842","DOIUrl":"https://doi.org/10.1109/DAC.1992.227842","url":null,"abstract":"The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132822844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
Application-driven design automation for microprocessor design 微处理器设计的应用驱动设计自动化
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227750
I. Pyo, Ching-Long Su, Ing-Jer Huang, K.-R. Pan, Y. Koh, C. Tsui, Hsu-Tsun Chen, G. Cheng, Shihming Liu, S. Wu, A. Despain
{"title":"Application-driven design automation for microprocessor design","authors":"I. Pyo, Ching-Long Su, Ing-Jer Huang, K.-R. Pan, Y. Koh, C. Tsui, Hsu-Tsun Chen, G. Cheng, Shihming Liu, S. Wu, A. Despain","doi":"10.1109/DAC.1992.227750","DOIUrl":"https://doi.org/10.1109/DAC.1992.227750","url":null,"abstract":"The authors present an overview of the application-driven design automation system (ADAS) for microprocessor design. ADAS accepts a specification of the instruction set architecture as input, and produces both layout specified in Caltech Intermediate Form, and a reorder table for the language compiler as output. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation. Another goal of the project is to determine the feasibility of applying formal methodology to design automation and the usefulness of formal syntax and semantics in defining the meaning of specifications. The system implementation on a real industrial example, the TDY-43 processor, is discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A new model for improving symbolic product machine traversal 改进符号产品机器遍历的新模型
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227812
G. Cabodi, P. Camurati, Fulvio Corno, S. Gai, P. Prinetto, M. Reorda
{"title":"A new model for improving symbolic product machine traversal","authors":"G. Cabodi, P. Camurati, Fulvio Corno, S. Gai, P. Prinetto, M. Reorda","doi":"10.1109/DAC.1992.227812","DOIUrl":"https://doi.org/10.1109/DAC.1992.227812","url":null,"abstract":"The authors present algorithms for traversing product machines which improve on the results of H. Cho et al. (1991), with a speedup ranging from 3 up to 6. New features include a model that generalizes the product machine, resulting in simpler and more efficient representations and computations, as well as optimizations in symbolic image computation. In the latter case, the speedup ranged from 1.5 to 4.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122655955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Circuit structure relations to redundancy and delay: the KMS algorithm revisited 电路结构与冗余和延迟的关系:重新审视KMS算法
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227828
A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Circuit structure relations to redundancy and delay: the KMS algorithm revisited","authors":"A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/DAC.1992.227828","DOIUrl":"https://doi.org/10.1109/DAC.1992.227828","url":null,"abstract":"K. Keutzer et al. (see IEEE Trans. on Comput.-Aided Des., vol.10, no.4, p.427-35 (1991)) have presented an algorithm, known as the KMS algorithm, that derives an equivalent irredundant circuit implementation from a given redundant high-performance circuit, with no increase in delay measured using viability analysis. The authors resolve the main bottlenecks in the KMS algorithm, arising due to an iterative loop of timing analysis, gate duplications, and redundancy removal. A circuit structure property based on path lengths is related to testability and delay. Based on this relationship, an efficient implementation of the KMS algorithm is presented. It consists of the transformation of any Boolean network to an equivalent circuit structure on which a single redundancy removal achieves the same effect as the original KMS algorithm.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129776104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
New models for four- and five-layer channel routing 四层和五层通道路由的新模型
[1992] Proceedings 29th ACM/IEEE Design Automation Conference Pub Date : 1992-07-01 DOI: 10.1109/DAC.1992.227817
Tai-Tsung Ho
{"title":"New models for four- and five-layer channel routing","authors":"Tai-Tsung Ho","doi":"10.1109/DAC.1992.227817","DOIUrl":"https://doi.org/10.1109/DAC.1992.227817","url":null,"abstract":"The author proposes two routing models for the four- and the five-layer routing environments based on the HHVH and HHVHH models, respectively. The layers for horizontal routing and the other for vertical routing are referred to as H and V layers, respectively. Since more layers are available for horizontal routing in the proposed models and the introduced via-violations in the new models are appropriately handled, the routing performance of the proposed multilayer router has outperformed all existing multilayer routers in the four- and five-layer routing environments. The experimental results are given and one detailed five-layer routing solution is outlined. The extension to a general multilayer router is discussed.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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