The role of long and short paths in circuit performance optimization

Abstract

The authors consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To develop the timing of the circuit, they use a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physical level, the problem is that of applying transistor sizing and delay buffer insertion to achieve specified upper bounds on clock period and latency. Experimental results are presented that reflect the complexity of the optimization problem. The clock period determination can also be extended to circuits with feedbacks.<>