Certified timing verification and the transition delay of a logic circuit

S. Devadas, K. Keutzer, S. Malik, Albert R. Wang
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引用次数: 85

Abstract

The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification.<>
逻辑电路的认证时间验证和转换延迟
研究了电路的过渡延迟。结果表明,即使在电路中存在任意单调加速时,电路的跃迁延迟也可以不同于浮动延迟。利用这一结果推导出了直接计算电路过渡延迟的程序。给出了将过渡延迟计算方法应用于若干基准算例的实验结果。这个程序最实际的好处是,它不仅导致了延迟计算,而且还产生了一个矢量序列,可以进行时序模拟,以证明静态时序验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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