{"title":"Certified timing verification and the transition delay of a logic circuit","authors":"S. Devadas, K. Keutzer, S. Malik, Albert R. Wang","doi":"10.1109/DAC.1992.227744","DOIUrl":null,"url":null,"abstract":"The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification.<<ETX>>","PeriodicalId":162648,"journal":{"name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"85","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1992.227744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 85
Abstract
The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating delay even in the presence of arbitrary monotonic speedups in the circuit. This result is used to derive a procedure which directly computes the transition delay of a circuit. Experimental results of applying the transition delay computation procedure to a number of benchmark examples are given. The most practical benefit of this procedure is that it not only results in a delay calculation but also produces a vector sequence that may be timing simulated to certify static timing verification.<>