2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)最新文献_第5页

Heavy ion irradiation of floating gate memory cells 浮门记忆细胞的重离子辐照

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309964

G. Cellere, A. Paccagnella, P. Caprara, A. Visconti

引用次数: 0

Low-K cu damascene interconnection leakage and process induced damage assessment 低钾铜damascene互连泄漏及工艺损伤评估

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309966

P. Aum

引用次数: 0

Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ? 用SON工艺实现的高性能双栅MOSFET:我们如何解决GAA SON的设计和工艺挑战?

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309913

P. Coronel, S. Harrison, R. Cerutti, S. Monfray, S. Skotnicki

{"title":"Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ?","authors":"P. Coronel, S. Harrison, R. Cerutti, S. Monfray, S. Skotnicki","doi":"10.1109/ICICDT.2004.1309913","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309913","url":null,"abstract":"Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very high Ion/Ioff trade off. Drive currents of 1954/spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333/spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported. After this GAA planar device demonstration, we are looking for his optimization in consideration of the future technologic node challenges: We define a new architecture for GAA and DG device in order to minimize the overlap capacitance, to use a SOI substrate and to create a GAA circuit with the same layout density than bulk. We develop a new concept of Metal gate and/or High-K integration in MOSFET: the PRETCH (Poly Replacement Through Contact Hole) to allow the best compromise between the mobility, and the Vt adjust for the future device generation. The first demonstration of the PRETCH integration was done on bulk CMOS.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The development of dual gate poly scheme with plasma nitrided gate oxide for mobile high performance DRAMs: plasma process monitoring and the correlation with electrical results 移动高性能dram用等离子体氮化栅极氧化物双栅方案的开发:等离子体过程监测及其与电学结果的相关性

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309948

Sug-hun Hong, Taek-Soo Jeon, Bonwon Koo, Seok-Hun Hyun, Yun-Seung Shin, U-In Chung, June Moon

引用次数: 4

Performances of Si nanocrystal memories obtained by by CVD and their potentialities to further scaling of non-volatile memories 化学气相沉积法获得的硅纳米晶存储器的性能及其在非易失性存储器进一步扩展方面的潜力

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309902

Cosimo Gerardi, B. DeSalvo, S. Lombardo, Thierry Baron

引用次数: 6

Energy dependence of vacuum-ultraviolet-induced radiation damage to electronic materials 真空紫外线对电子材料辐射损伤的能量依赖性

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309972

J. Lauer, J. Shohet, R. Hansen, R. D. Bathke, B. Grierson, G. Upadhyaya, K. Kukkady, J. Kalwitz

引用次数: 1

Multi gated device architectures advances, advantages and challenges 多门控器件体系结构的进步、优势和挑战

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309916

L. Mathew, Yang Du, A. Thean, M. Sadd, A. Vandooren, C. Parker, T. Stephens, R. Mora, R. Rai, M. Zavala, D. Sing, S. Kalpai, J. Hughes, R. Shimer, S. Jallepalli, G. Workman, B. White, B. Nguyen, A. Mogab

引用次数: 3

Atomic layer deposition of high-k thin films for gate and capacitor dielectrics 栅极和电容电介质用高k薄膜的原子层沉积

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309960

Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford

{"title":"Atomic layer deposition of high-k thin films for gate and capacitor dielectrics","authors":"Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford","doi":"10.1109/ICICDT.2004.1309960","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309960","url":null,"abstract":"Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation 阈值电压不稳定和等离子体诱导的多晶硅/HfO/sub - 2/器件损伤——氘掺入的积极影响

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309957

H. Tseng, M. Ramón, L. Hebert, P. Tobin, D. Triyoso, S. Kalpat, J. Grant, Z.X. Jiang, D. Gilmer, D. Menke, W. Taylor, O. Adetutu, B. White

引用次数: 4

Advanced transistor structures for high performance microprocessors 用于高性能微处理器的先进晶体管结构

2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Pub Date : 2004-10-04 DOI: 10.1109/ICICDT.2004.1309909

M. Horstmann, D. Greenlaw, T. Feudel, Andy Wei, K. Frohberg, G. Burbach, M. Gerhardt, Markus Lenski, R. Stephan, K. Wieczorek, Matthias Schaller, J. Hohage, H. Ruelke, J. Klais, P. Huebler, Scott Luning, R. Bentum, G. Grasshoff, C. Schwan, Jon D. Cheek, J. Buller, S. Krishnan, M. Raab, N. Kepler

引用次数: 2