Highly performant double gate MOSFET realized with SON process: how we address the design and process for the GAA SON challenges ?

Utilizing the SON (Silicon On Nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (High Performance and Low Power) with very high Ion/Ioff trade off. Drive currents of 1954/spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333/spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained @1.2V with Tox = 20A and Lgate = 70nm. DIBL is very well controlled, measured below 60mV for gates as short as 40nm. These features place our devices among the most performant ever reported. After this GAA planar device demonstration, we are looking for his optimization in consideration of the future technologic node challenges: We define a new architecture for GAA and DG device in order to minimize the overlap capacitance, to use a SOI substrate and to create a GAA circuit with the same layout density than bulk. We develop a new concept of Metal gate and/or High-K integration in MOSFET: the PRETCH (Poly Replacement Through Contact Hole) to allow the best compromise between the mobility, and the Vt adjust for the future device generation. The first demonstration of the PRETCH integration was done on bulk CMOS.