Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford
{"title":"栅极和电容电介质用高k薄膜的原子层沉积","authors":"Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford","doi":"10.1109/ICICDT.2004.1309960","DOIUrl":null,"url":null,"abstract":"Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Atomic layer deposition of high-k thin films for gate and capacitor dielectrics\",\"authors\":\"Y. Senzaki, H. Chatham, S. Park, L. Bartholomew, T. Lo, Y. Okuyama, C. Barelli, C. Tousseau, T. Fleming, B. Ford\",\"doi\":\"10.1109/ICICDT.2004.1309960\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309960\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309960","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Atomic layer deposition of high-k thin films for gate and capacitor dielectrics
Atomic layer deposition (ALD) has gained acceptance as a thin film deposition technique in the semiconductor device manufacturing due to the stringent requirements of thickness uniformity, thermal budget, and step coverage over aggressive advanced IC device structures. We have developed unique ALD processes to deposit multi-component thin films such as HfSiO/sub x/ for high-k gate dielectric applications by co-injection of Hf and Si precursors. This process enables the formation of homogeneous single-layer hafnium silicate films as deposited. In contrast, the commonly used nanolaminate technique (i.e., an alternating stack of HfO/sub 2/ and SiO/sub 2/ layers) requires high temperature post-deposition annealing to interdiffuse the HfO/sub 2/ and SiO/sub 2/ to form a hafnium silicate film. We have also developed an Al/sub 2/O/sub 3/ batch ALD process on 300mm. Si (100) substrates using a multiwafer hot-wall reactor. Deposition of Al/sub 2/O/sub 3/ thin films from trimethylaluminum and ozone was accomplished using a 50-wafer batch system. For 4.6 nm thick Al/sub 2/O/sub 3/, excellent film thickness uniformity with a within-wafer (WIW) non-uniformity of <1.0% 1/spl sigma/ and a wafer to wafer (WTW) thickness non-uniformity of less than /spl plusmn/1.0% was achieved over a full batch.