Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第7页

A data alignment technique for improving cache performance 一种用于提高缓存性能的数据对齐技术

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628925

P. Panda, Hiroshi Nakamura, N. Dutt, A. Nicolau

引用次数: 20

Application of a testing framework to VHDL descriptions at different abstraction levels 测试框架在不同抽象层次上对VHDL描述的应用

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628935

M. Bacis, G. Buonanno, Fabrizio Ferrandi, F. Fummi, Luca Gerli, D. Sciuto

引用次数: 1

First test results of system level fault tolerant design validation through laser fault injection 首先通过激光故障注入验证了系统级容错设计的测试结果

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628919

W. Moreno, F. J. Falquez, J. Samson, T. Smith

{"title":"First test results of system level fault tolerant design validation through laser fault injection","authors":"W. Moreno, F. J. Falquez, J. Samson, T. Smith","doi":"10.1109/ICCD.1997.628919","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628919","url":null,"abstract":"Fault tolerant design validation tests through laser fault injection (LFI) have been carried out at the Center for Microelectronics Research (CMR) of the University of South Florida (USF) by a team of scientists and engineers led by Dr. Wilfrido Moreno with cooperation from the Space and Strategic Systems Operation (SASSO) of Honeywell, Inc. The technique, demonstrated by previous work at the CMR involves the precise application of a laser pulse tailored as to power, pulse width and frequency into a very large scale integrated circuit (VLSIC) which is a component of an operating computer capable of detecting, logging and recovering from a transient fault and then proceeding with its operation. The test vehicle is the radiation hardened 32-bit processor (RH32) developed by Honeywell for the Rome Laboratory of the United States Air Force and the Laser facility is the Laser Restructuring Laboratory (LRL) of the CMR built under a grant from the Defense Advanced Research Project Agency (DARPA). Two system level series of tests have been completed. The first one involved the verification of initial demo tests performed by others on an early version of the computer which was limited to verifying that the computer detected and logged a hardware error in the register file of the central processing unit (CPU). These tests were expanded to observe the incrementing of the error count register of the same chip as laser pulses were applied. During the second series of rests, and for the first time, the result was obtained of observing the processor detect a hardware error, log and correct it and then proceed with the present instruction. The previous being evident by the data entered by the processor in the statusing registers.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127434012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

PROPHID: a heterogeneous multi-processor architecture for multimedia PROPHID:用于多媒体的异构多处理器架构

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628864

J. Leijten, J. V. Meerbergen, A. Timmer, J. Jess

{"title":"PROPHID: a heterogeneous multi-processor architecture for multimedia","authors":"J. Leijten, J. V. Meerbergen, A. Timmer, J. Jess","doi":"10.1109/ICCD.1997.628864","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628864","url":null,"abstract":"PROPHID is a design method aiming at high-performance systems with a focus on high-throughput signal processing for multimedia applications. The processing and communication bandwidth requirements of such systems are very high. To obtain a good balance between performance, programmability and efficiency in terms of speed, area and power PROPHID uses a novel heterogeneous multi-processor architecture template which exploits task-level concurrency. A general purpose processor aimed at control-oriented tasks and low to medium-performance signal processing tasks, as well as application domain specific processors aimed at high-performance signal processing tasks are available in this template. Next to a central control-oriented bus a special high-throughput communication network is used to meet the high bandwidth requirements of the application domain specific processors. This paper discusses the characteristics and advantages of the PROPHID architecture showing that high performance is obtained by embedding multiple autonomous data-driven processors in a stream-based communication environment.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Allocation and data arrival design of hard real-time systems 硬实时系统的分配与数据到达设计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628900

D. Rhodes, W. Wolf

引用次数: 6

Comparison between nMOS pass transistor logic style vs. CMOS complementary cells nMOS通路晶体管逻辑方式与CMOS互补单元的比较

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628859

R. Mehrotra, Massoud Pedram, Xunwei Wu

引用次数: 7

Nonenumerative path delay fault coverage estimation with optimal algorithms 基于最优算法的非枚举路径延迟故障覆盖估计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628896

D. Kagaris, S. Tragoudas, D. Karayiannis

引用次数: 3

Design and performance evaluation of a cache assist to implement selective caching 缓存的设计和性能评估有助于实现选择性缓存

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628916

L. John, Akila Subramanian

引用次数: 35

Discrete drive selection for continuous sizing 离散驱动选择连续尺寸

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628856

R. Haddad, L. V. Ginneken, Narendra V. Shenoy

引用次数: 14

An evaluation of asynchronous and synchronous design for superscalar architectures 超标量体系结构异步与同步设计的评价

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628882

A. Davey, D. Lloyd

引用次数: 0