Nonenumerative path delay fault coverage estimation with optimal algorithms

D. Kagaris, S. Tragoudas, D. Karayiannis
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引用次数: 3

Abstract

A recent method proposed that a lower bound on the number of path delay faults excited by a given test set can be computed using a set independent lines that form a cut. For each line in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower bound to the number of excited path delay faults can be obtained by working on the respective subcircuits. A polynomial time algorithm is presented here for computing the maximum cardinality set of independent circuit lines. Experimental results show that the more the subcircuits the better the lower bound on the number of excited path delay faults is. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts C/sub i/. We propose a technique where only one C/sub i/ must be a cut. This scheme is based on novel algorithms, and results in more subcircuits than the previous one.
基于最优算法的非枚举路径延迟故障覆盖估计
最近提出了一种方法,可以使用一组独立的线来计算由给定测试集激发的路径延迟故障数量的下界。对于每条线路都定义了一个由包含线路的所有路径组成的子电路,并通过对各个子电路进行处理,可以获得激励路径延迟故障数量的下界。本文提出了一种计算独立电路最大基数集的多项式时间算法。实验结果表明,子电路越多,激励路径延迟故障个数的下界越好。更多的子电路只能以启发式的方式产生。建议考虑两个或两个以上的断线切割C/sub / i/。我们提出了一种技术,其中只有一个C/sub /必须是一个切割。该方案基于新颖的算法,并且比以前的方案产生更多的子电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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