First test results of system level fault tolerant design validation through laser fault injection

Abstract

Fault tolerant design validation tests through laser fault injection (LFI) have been carried out at the Center for Microelectronics Research (CMR) of the University of South Florida (USF) by a team of scientists and engineers led by Dr. Wilfrido Moreno with cooperation from the Space and Strategic Systems Operation (SASSO) of Honeywell, Inc. The technique, demonstrated by previous work at the CMR involves the precise application of a laser pulse tailored as to power, pulse width and frequency into a very large scale integrated circuit (VLSIC) which is a component of an operating computer capable of detecting, logging and recovering from a transient fault and then proceeding with its operation. The test vehicle is the radiation hardened 32-bit processor (RH32) developed by Honeywell for the Rome Laboratory of the United States Air Force and the Laser facility is the Laser Restructuring Laboratory (LRL) of the CMR built under a grant from the Defense Advanced Research Project Agency (DARPA). Two system level series of tests have been completed. The first one involved the verification of initial demo tests performed by others on an early version of the computer which was limited to verifying that the computer detected and logged a hardware error in the register file of the central processing unit (CPU). These tests were expanded to observe the incrementing of the error count register of the same chip as laser pulses were applied. During the second series of rests, and for the first time, the result was obtained of observing the processor detect a hardware error, log and correct it and then proceed with the present instruction. The previous being evident by the data entered by the processor in the statusing registers.