Application of a testing framework to VHDL descriptions at different abstraction levels

Abstract

The test problem increasingly affects the system design process and related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. The paper presents a global toolset architecture for testability analysis and test pattern generation. Three abstraction levels are considered in this design flow, from the behavioral specifications, through RTL descriptions, down to gate level. In all these phases, VHDL is chosen as the referring description language. The paper then presents an application scenario, detailing the results achieved by the proposed methodology.