Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第6页

High performance CMOS circuit techniques for the G-4 S/390 microprocessor g - 4s /390微处理器的高性能CMOS电路技术

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628875

J. Warnock, L. Sigal, B. Curran, Y. Chan

引用次数: 1

Is wireless data dead? 无线数据死了吗?

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628927

R. Katz

引用次数: 0

A 400 MHz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor 用于IBM S/390级微处理器的400 MHz, 144 Kb CMOS ROM宏

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628876

A. Tuminaro

{"title":"A 400 MHz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor","authors":"A. Tuminaro","doi":"10.1109/ICCD.1997.628876","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628876","url":null,"abstract":"A high performance 2 K/spl times/72 CMOS ROM for fetching most frequently used complex instruction code in a high speed S/390-class microprocessor is described in this paper. The ROM has a nominal access/cycle time performance of 2.3 ns/2.5 ns and is physically organized as 128 word lines by 1152 bit lines. Personalization is done at the gate level of the device. The technology used was the IBM CMOS6S technology which features Leff=0.2 /spl mu/m and a 2.5 V power supply. Several innovative circuit techniques were employed to achieve the aggressive ROM access/cycle time performance. Each stage in the access path is dynamically reset thereby avoiding the use of a centralized clock circuit and also yielding the benefit of a fast cycle time. The ROM macro features a dynamic reference source and sense amplifier which allows single ended sensing of a bit line. Also the sense amplifier clock is generate from the decoded word line through an OR tree. Hence the access time performance tracks with the loading on the decoded word line. The macro physical area is 3300/spl times/715 /spl mu/m/sup 2/ and the array cell has an area of 2/spl times/2 /spl mu/m/sup 2/. Less than 10% of the ROM macro area is designated to ABIST circuitry which allows for extensive test coverage.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116013594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Critical voltage transition logic: an ultrafast CMOS logic family 临界电压转换逻辑:一个超快的CMOS逻辑家族

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628946

Zhang‐ming Zhu, B. Carlson

引用次数: 9

Memory traffic and data cache behavior of an MPEG-2 software decoder MPEG-2软件解码器的内存流量和数据缓存行为

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628903

Peter Soderquist, M. Leeser

{"title":"Memory traffic and data cache behavior of an MPEG-2 software decoder","authors":"Peter Soderquist, M. Leeser","doi":"10.1109/ICCD.1997.628903","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628903","url":null,"abstract":"The authors investigate the impact of multimedia applications on the cache behavior of desktop systems. Specifically they consider the memory bandwidth and data cache challenges associated with MPEG-2 software decoding. Recent extensions to instruction set architectures, including Intel's MMX, address the computational aspects of MPEG decoding. The large amount of data traffic generated, however has received little attention. Standard data caches consistently generate an excess of cache-memory traffic. Varying basic cache parameters only reduces traffic to double the minimum required at best. Incremental changes in cache size have a negligible effect for most feasible values. Increasing set associativity yields rapidly diminishing returns, and manipulating line size is similarly unproductive. Achieving higher efficiency requires understanding the composition and behavior of the decoder data set. They present a model of MPEG-2 decoder memory behavior and describe how to exploit this knowledge to minimize required memory bandwidth. Their results show that simply eliminating one component, video output data, from the cache can reduce traffic by as much as 50 percent.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"84 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Timed binary decision diagrams 定时二元决策图

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628894

Zhongcheng Li, Yuhong Zhao, Y. Min, R. Brayton

引用次数: 2

A repeater optimization methodology for deep sub-micron, high-performance processors 一种用于深亚微米高性能处理器的中继器优化方法

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628945

David Li, Andrew Pua, Pranjal Srivastava, U. Ko

引用次数: 32

A pulse-to-static conversion latch with a self-timed control circuit 具有自定时控制电路的脉冲-静态转换锁存器

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628943

W. Hwang, R. Joshi, W. Henkels

{"title":"A pulse-to-static conversion latch with a self-timed control circuit","authors":"W. Hwang, R. Joshi, W. Henkels","doi":"10.1109/ICCD.1997.628943","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628943","url":null,"abstract":"The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with SRCMOS test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. An experimental 64-bit latch array and self-timed control macro, designed for 2.5 V-0.5 /spl mu/m CMOS technology, has been successfully fabricated and tested. The full circuit occupies an area of 1.704 mm/spl times/0.07 mm, and the size of latch bit cell is 21.6 /spl mu/m/spl times/70 /spl mu/m. Experimental results have shown the conversion latch to function properly, capturing 1.2 ns output pulses from an SRCMOS register file, and properly converting them to static levels. The measured delay from global clock to static output was 725 ps.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130136842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Estimation of maximum power for sequential circuits considering spurious transitions 考虑杂散跃迁的顺序电路最大功率估计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628948

Chuan-Yu Wang, K. Roy

{"title":"Estimation of maximum power for sequential circuits considering spurious transitions","authors":"Chuan-Yu Wang, K. Roy","doi":"10.1109/ICCD.1997.628948","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628948","url":null,"abstract":"With the high demand for reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maximum current, and hence, the maximum power, is NP-complete. Even for circuits with small number of primary inputs (PIs), it is CPU time intensive to conduct efficiently search in the input vector space. The authors present an automatic test generation (ATG) based technique to efficiently generate tight lower bounds of the maximum instananeous power for CMOS sequential circuits under non-zero gate delays. Power dissipation due to spurious transitions has been considered by incorporating static timing analysis into the estimation process. Experiments were performed on ISCAS and MCNC benchmarks. Results show that the ATG-based technique is superior to the traditional simulation-based technique in both speed and performance. On average, for sequential circuits having over 10,000 gates (ISCAS-89 benchmarks), the ATG-based approach executes 981 times faster, and generates a lower bound which is 1.8 times better compared to simulation based approaches.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125390215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Power driven partial scan 功率驱动部分扫描

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628933

Jing-Yang Jou, Ming-Chang Nien

引用次数: 3