Critical voltage transition logic: an ultrafast CMOS logic family

Abstract

The authors present a new kind of CMOS logic circuit that has a different structure and different operation mechanism compared to the existing logic circuits. Its unique delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Gate outputs are preconditioned to a voltage level between V/sub dd/ and V/sub ss/ using a new clocking scheme and circuit design. They give a buffer design example which is about 6.5 times faster than the conventional buffer. The total energy consumed by the new circuit structure is slightly more than conventional CMOS domino logic; however the energy-delay product is smaller.