A 400 MHz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor

Abstract

A high performance 2 K/spl times/72 CMOS ROM for fetching most frequently used complex instruction code in a high speed S/390-class microprocessor is described in this paper. The ROM has a nominal access/cycle time performance of 2.3 ns/2.5 ns and is physically organized as 128 word lines by 1152 bit lines. Personalization is done at the gate level of the device. The technology used was the IBM CMOS6S technology which features Leff=0.2 /spl mu/m and a 2.5 V power supply. Several innovative circuit techniques were employed to achieve the aggressive ROM access/cycle time performance. Each stage in the access path is dynamically reset thereby avoiding the use of a centralized clock circuit and also yielding the benefit of a fast cycle time. The ROM macro features a dynamic reference source and sense amplifier which allows single ended sensing of a bit line. Also the sense amplifier clock is generate from the decoded word line through an OR tree. Hence the access time performance tracks with the loading on the decoded word line. The macro physical area is 3300/spl times/715 /spl mu/m/sup 2/ and the array cell has an area of 2/spl times/2 /spl mu/m/sup 2/. Less than 10% of the ROM macro area is designated to ABIST circuitry which allows for extensive test coverage.