Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第10页

Crosstalk-constrained maze routing based on Lagrangian relaxation 基于拉格朗日松弛的串扰约束迷宫路径

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628931

H. Zhou, Martin D. F. Wong

引用次数: 12

Real-time operating systems for embedded computing 嵌入式计算的实时操作系统

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628899

Yanbing Li, M. Potkonjak, W. Wolf

引用次数: 30

Intelligent RAM (IRAM): the industrial setting, applications, and architectures 智能RAM (IRAM):工业设置、应用和架构

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628842

D. Patterson, K. Asanović, Aaron B. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, David R. Martin, S. Perissakis, Randi Thomas, N. Treuhaft, K. Yelick

引用次数: 62

A new approach for initialization sequences computation for synchronous sequential circuits 同步顺序电路初始化序列计算的新方法

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628898

Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda, Giovanni Squillero

引用次数: 10

A novel test set design for parametric testing of analog and mixed-signal circuits 一种用于模拟和混合信号电路参数化测试的新型测试集设计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628911

Jin Chen, A. Ramachandran

引用次数: 3

Built-in self test for content addressable memories 内置自我测试内容可寻址存储器

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628848

Y. Kang, J. Lee, Sungho Kang

引用次数: 3

Development of a high bandwidth merged logic/DRAM multimedia chip 高带宽逻辑/DRAM融合多媒体芯片的研制

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628880

W. Luk, Y. Katayama, W. Hwang, M. Wordeman, T. Kirihata, A. Satoh, S. Munetoh, H. Wong, B. El-Kareh, P. Xiao, R. Joshi

{"title":"Development of a high bandwidth merged logic/DRAM multimedia chip","authors":"W. Luk, Y. Katayama, W. Hwang, M. Wordeman, T. Kirihata, A. Satoh, S. Munetoh, H. Wong, B. El-Kareh, P. Xiao, R. Joshi","doi":"10.1109/ICCD.1997.628880","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628880","url":null,"abstract":"This paper describes the design methodology and the implementation of a merged logic/DRAM multimedia chip. The design is based on 0.25 micron DRAM-based CMOS technology with 4-layers of metal with device performance enhancement. Details of the architecture and system design of the multi-media was described in Katayama et. al. (1996). The present chip consists of 64 Mb of synchronous DRAM which is organized in two banks of eight 8 Mb SDRAM macros, a gate-array memory control and bus control unit, a custom-designed 8/spl times/32-bit parallel graphic processor, a 64-bit parallel ports for data transfer to/from the host processor bus, a 32-bit serial port for video display, and on-chip PLL. The multi-media co-processor chip provides high-density unified memory, high bus bandwidth (4.3 GB/s peak) and 1+GB/s BITBLT processing functions for an external host processor. The current design, floorplan and layout are structured in a way that, we believe, will provide a general framework for other merged logic/DRAM, ASIC+DRAM design for system scale integration.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125838001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Pseudo-random pattern testing of bridging faults 桥接故障的伪随机模式测试

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628849

N. Touba, E. McCluskey

{"title":"Pseudo-random pattern testing of bridging faults","authors":"N. Touba, E. McCluskey","doi":"10.1109/ICCD.1997.628849","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628849","url":null,"abstract":"While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage in a built-in self-test (BIST) environment. Bridging faults are generally more random pattern testable than stuck-at faults, but examples are shown to illustrate that some bridging faults can be much less random pattern testable than stuck-at faults. A fast method for identifying these random-pattern-resistant bridging faults is described. State-of-the-art test point insertion techniques, which are based on the stuck-at fault model, are inadequate. Data is presented which indicates that even after inserting test points that result in 100% single stuck-at fault coverage, many bridging faults are still not detected. A test point insertion procedure that targets both single stuck-at faults and non-feedback bridging faults is presented. It is shown that by considering bath types of faults when selecting the location for test points, higher fault coverage can be obtained with little or no increase in overhead. Thus, the test point insertion procedure described here is a low-cost way to improve the quality of built-in self-test.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Partitioning under timing and area constraints 在时间和面积约束下进行分区

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628929

G. Tumbush, D. Bhatia

引用次数: 5

A high-frequency custom CMOS S/390 microprocessor 高频定制CMOS S/390微处理器

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-07-01 DOI: 10.1109/ICCD.1997.628874

C. Webb, J. Liptay

引用次数: 56