Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第5页

Elastic history buffer: a low-cost method to improve branch prediction accuracy 弹性历史缓冲:一种低成本提高分支预测精度的方法

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628853

Maria-Dana Tarlescu, K. B. Theobald, G. Gao

引用次数: 27

Dynamic bounding of successor force computations in the force directed list scheduling algorithm 力有向表调度算法中后继力计算的动态边界

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628949

S. Govindarajan, R. Vemuri

{"title":"Dynamic bounding of successor force computations in the force directed list scheduling algorithm","authors":"S. Govindarajan, R. Vemuri","doi":"10.1109/ICCD.1997.628949","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628949","url":null,"abstract":"The well known Force Directed List Scheduling (FDLS) Algorithm uses a rigorous priority function called the Force of an operation. The force of an operation is governed by two components, namely the self-force of an operation and its successors' forces. The successor force in turn is governed by the self-force of all the descendants of the operation. FDLS is computationally intensive in its force calculations. For data flow dominated designs, a major portion of the FDLS execution time is spent in the computation of successor forces. However in this paper we observe that it is not always necessary to compute successor forces till the last successor level. We have shown in this paper that there usually exists a stabilization point after which successor force computations would not affect the quality of the schedule produced. This paper presents a concept of stability to show that it is possible to dynamically bound the successor force calculations in FDLS, up to a certain level of descendants. We have measured the performance of FDLS for a suite of high level synthesis benchmarks. Results presented in the paper show considerable reduction in execution time for the same schedule quality. This would allow a high-level synthesis tool to perform better design space exploration.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"13 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120914314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Synthesizing iterative functions into delay-insensitive tree circuits 将迭代函数合成为延迟不敏感的树形电路

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628883

Fu-Chiung Cheng

引用次数: 3

If software is king for systems-on-silicon, what's new in compilers? 如果软件是硅上系统之王，那么编译器有什么新变化呢?

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628889

N. Dutt, S. Malik, L. Augusteijn, B. Fu, A. Nicolau, C. Polychronopoulos

引用次数: 0

CMOS gate delay models for general RLC loading 通用RLC加载的CMOS门延迟模型

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628872

Ravishankar Arunachalam, F. Dartu, L. Pileggi

引用次数: 64

An efficient multi-way algorithm for balanced partitioning of VLSI circuits VLSI电路平衡划分的一种高效多路算法

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628928

X. Tan, J. Tong, P. Tan, N. Park, F. Lombardi

引用次数: 11

Novel simulation of deep-submicron MOSFET circuits 深亚微米MOSFET电路的新型仿真

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628850

S. Bruma, R. Otten

引用次数: 2

Time-stamped transition density for the estimation of delay dependent switching activities 时延相关切换活动估计的时间戳跃迁密度

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628851

Hoon Choi, S. Hwang

{"title":"Time-stamped transition density for the estimation of delay dependent switching activities","authors":"Hoon Choi, S. Hwang","doi":"10.1109/ICCD.1997.628851","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628851","url":null,"abstract":"We propose a new method to improve the accuracy of the transition density for the estimation of delay dependent switching activities in combinational circuits. In the previous method, glitching sensitivity concept was defined and used to modify the transition density so as to generate and propagate the glitch. To account for the inertial delay effect, the same technique that is commonly used in logic simulators to filter out unacceptably short pulses was used. However, since it does not keep transition density at each occurrence time separately, it is not adequate for the accurate estimation of glitch and inertial delay effect. In addition, it underestimates the difference between probabilistic property of the transition density and the deterministic property of signals in logic simulations in computing inertial delay effect. We describe the problems of the previous methods and propose a new method called time-stamped transition density to solve the problems. We also show the extensions of the method to consider possible delay variation due to imperfections in the manufacturing process. The experimental results demonstrate the validity of our proposed method.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"404 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130103073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A survey of techniques for formal verification of combinational circuits 组合电路形式验证技术综述

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628907

J. Jain, A. Narayan, M. Fujita, A. Sangiovanni-Vincentelli

引用次数: 18

Design optimization for high-speed per-address two-level branch predictors 高速每地址两级分支预测器的设计优化

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628854

I-Cheng K. Chen, Chih-Chieh Lee, M. Postiff, T. Mudge

{"title":"Design optimization for high-speed per-address two-level branch predictors","authors":"I-Cheng K. Chen, Chih-Chieh Lee, M. Postiff, T. Mudge","doi":"10.1109/ICCD.1997.628854","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628854","url":null,"abstract":"Per-address two-level branch predictors have been shown to be among the best predictors and have been implemented in current microprocessors. However, as the cycle time of modern microprocessors continues to decrease, the implementation of set-associative per-address two-level branch predictors will become more difficult. Instead, direct-mapped designs may be more attractive. In this paper, we investigate an alternative implementation of the per-address two-level predictor referred to as the tagless, direct-mapped predictor which is simpler and has faster access time. The tagless predictor can offer comparable performance to current set-associative designs since removal of tags allows more resources to be allocated for the predictor and branch target buffer (BTB). Removal of tags also decouples the per-address predictors from the BTB, thus allowing the two components to be optimized individually. Furthermore, our results show that this tagless implementation is more accurate because it handles conflict misses in the branch history table better. Finally, we examine the system cost-benefit for tagless per-address predictors across a wide design space using equal-cost contours. We study the sensitivity of performance to the workloads by comparing results from the Instruction Benchmark Suite (IBS) and SPEC CINT95. Our work provides principles and quantitative parameters for optimal configurations of such predictors.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124519365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2