Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第4页

Channel segmentation design for symmetrical FPGAs 对称fpga的信道分割设计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628914

Wai-Kei Mak, D. F. Wong

引用次数: 10

On complexity reduction of FIR digital filters using constrained least squares solution 用约束最小二乘方法降低FIR数字滤波器的复杂度

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628868

K. Muhammad, K. Roy

引用次数: 5

Practical advances in asynchronous design 异步设计的实际进展

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628936

E. Brunvand, S. Nowick, K. Yun

引用次数: 2

Intertwined development and formal verification of a 60/spl times/ bus model 60/spl次/总线模型的交织开发和正式验证

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628845

Matt Kaufmann, C. Pixley

引用次数: 3

Enhanced compression techniques to simplify program decompression and execution 增强的压缩技术，简化程序解压缩和执行

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628865

M. Breternitz, Roger Smith

引用次数: 10

Optimal clock period clustering for sequential circuits with retiming 带重定时的顺序电路的最佳时钟周期聚类

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628858

P. Pan, Arvind K. Karandikar, C. Liu

引用次数: 51

Synthesis of delay verifiable sequential circuits using partial enhanced scan 部分增强扫描延时可验证顺序电路的合成

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628934

R. Tekumalla, P. R. Menon

引用次数: 5

Vector restoration based static compaction of test sequences for synchronous sequential circuits 基于矢量恢复的同步时序电路测试序列静态压缩

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628895

I. Pomeranz, S. Reddy

引用次数: 108

Built-in temperature sensors for on-line thermal monitoring of microelectronic structures 内置温度传感器，用于微电子结构的在线热监测

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628909

Karim Arabi, B. Kaminska

引用次数: 29

Design and implementation of low-power digit-serial multipliers 低功耗数字串行乘法器的设计与实现

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628867

Yun-Nan Chang, J. Satyanarayana, K. Parhi

{"title":"Design and implementation of low-power digit-serial multipliers","authors":"Yun-Nan Chang, J. Satyanarayana, K. Parhi","doi":"10.1109/ICCD.1997.628867","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628867","url":null,"abstract":"Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel design methodology is presented which permits bit-level pipelining of the digit-serial architectures. This achieves sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for transformed multipliers with smaller digit-sizes (/spl les/4), the singly-redundant multiplier consumes the least power and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2 W), where W represents the word-length. The proposed digit-serial multipliers consume on an average 20% lower power than the traditional digit-serial architectures for the non-pipelined case, and about 5-15 times lower power for the bit-level pipelined case. Also, modified Booth (1951) recoding is applied to transformed multipliers and it is found that the recoded multipliers consume about 22% lower power than the transformed multipliers without recoding.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121946271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22