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A parallel circuit-partitioned algorithm for timing driven cell placement 一种并行电路分块算法，用于定时驱动单元放置
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628930
J. Chandy, P. Banerjee
{"title":"A parallel circuit-partitioned algorithm for timing driven cell placement","authors":"J. Chandy, P. Banerjee","doi":"10.1109/ICCD.1997.628930","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628930","url":null,"abstract":"Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing based placement has minimized area, but with deep submicron design, minimizing wirelength delay is also needed. The algorithm discussed in this paper is the first parallel algorithm for timing driven placement. We have used a very accurate Elmore delay model which is more complete intensive and hence the need for parallel placement is more apparent. Parallel placement is also needed for very large circuits that may not fit in the memory of a single processor. Therefore, our algorithm is circuit partitioned and can handle arbitrary large circuits on distributed memory multiprocessors. The algorithm, called mpi PLACE, has been tested on several large benchmarks on a variety of parallel architectures.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BIST-based fault diagnosis in the presence of embedded memories 嵌入式存储器下基于bist的故障诊断
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628847
J. Savir
{"title":"BIST-based fault diagnosis in the presence of embedded memories","authors":"J. Savir","doi":"10.1109/ICCD.1997.628847","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628847","url":null,"abstract":"An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127731531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model TITAC-2:基于可扩展延迟不敏感模型的32位异步微处理器
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628881
A. Takamura, M. Kuwako, Masashi Imai, T. Fujii, M. Ozawa, Izumi Fukasaku, Y. Ueno, T. Nanya
{"title":"TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model","authors":"A. Takamura, M. Kuwako, Masashi Imai, T. Fujii, M. Ozawa, Izumi Fukasaku, Y. Ueno, T. Nanya","doi":"10.1109/ICCD.1997.628881","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628881","url":null,"abstract":"Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3 MIPS using the Dhrystone V2.1 benchmark.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128048367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Optimizing CMOS implementations of the C-element 优化c元件的CMOS实现
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628941
M. Shams, J. Ebergen, M. Elmasry
{"title":"Optimizing CMOS implementations of the C-element","authors":"M. Shams, J. Ebergen, M. Elmasry","doi":"10.1109/ICCD.1997.628941","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628941","url":null,"abstract":"The C-element is one of the most frequently used primitives in asynchronous control circuits. This paper introduces various single-rail and double-rail implementations of the C-element, explains ways to optimize their performance and compares them with respect to energy and speed in a micropipeline control circuit environment. The issue of divergence of the complementary outputs in the double-rail implementations is also discussed.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121409959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A TSC evaluation function for combinational circuits 一种用于组合电路的TSC评估函数
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628921
C. Bolchini, D. Sciuto, F. Salice
{"title":"A TSC evaluation function for combinational circuits","authors":"C. Bolchini, D. Sciuto, F. Salice","doi":"10.1109/ICCD.1997.628921","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628921","url":null,"abstract":"The paper presents an innovative evaluation function for circuits with on-line detecting properties, which considers other aspects beyond area overhead. In particular, this function takes into account the probability of detecting a fault, once it occurs, with respect to the network structure and the application of input configurations. Different implementations of the same device designed to have TSC properties are compared with respect to this innovative evaluation function.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor Alpha 21264微处理器总线接口单元的正式实现验证
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628844
G. Bischoff, K. Brace, Samir Jain, R. Razdan
{"title":"Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor","authors":"G. Bischoff, K. Brace, Samir Jain, R. Razdan","doi":"10.1109/ICCD.1997.628844","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628844","url":null,"abstract":"In this paper we present our method of formal verification of the transistor implementation of the Bus Interface Unit (BIU) of the Alpha 21264 microprocessor. We compare the logical description compiled from the Register Transfer Level (RTL) against that extracted from the custom-designed transistor-level schematics. BOVE, our BDD-based verification tool, does not require latch-to-latch correspondence, thus allowing the RTL to be more stable during the design process and giving the schematic designers freedom to implement race and timing optimizations. A unique \"retiming\" comparison algorithm efficiently compares partitions that include multiple pipeline stages, retiming optimizations and precharge logic. BOVE also verifies small finite-state machines that have different state encodings in the RTL and schematic.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129578808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Benchmarking and analysis of architectures for CAD applications 对CAD应用架构进行基准测试和分析
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628937
A. Mehrotra, S. Qadeer, R. Ranjan, R. Katz
{"title":"Benchmarking and analysis of architectures for CAD applications","authors":"A. Mehrotra, S. Qadeer, R. Ranjan, R. Katz","doi":"10.1109/ICCD.1997.628937","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628937","url":null,"abstract":"The SPEC benchmark system has traditionally been used for evaluating computer architectures. However, this system is too general and does not accurately reflect the performance of architectures on domain-specific applications. Moreover the CPU95 benchmark suite used in the SPEC system is compute-intensive, while many important domains of applications have memory intensive algorithms. In this work, we present a benchmarking methodology for such an application domain-CAD for VLSI design. We have created a benchmark suite consisting of CAD applications from each stage in a typical VLSI design flow. To exercise the memory organization, each application is run on a sequence of input designs of increasing size. We observed that increasing the input size causes non-monotonic variations in the performance of different machines. We simulate the caches of the benchmarked architectures to assess the effect of memory organization on performance.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dynamic reordering in a breadth-first manipulation based BDD package: challenges and solutions 基于广度优先操作的BDD包中的动态重排序:挑战和解决方案
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628893
R. Ranjan, W. Gosti, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Dynamic reordering in a breadth-first manipulation based BDD package: challenges and solutions","authors":"R. Ranjan, W. Gosti, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCD.1997.628893","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628893","url":null,"abstract":"The breadth-first manipulation technique has proven effective in dealing with very large sized BDDs. However, until now the lack of dynamic variable reordering has remained an obstacle in its acceptance. The goal of the work is to provide efficient techniques to address this issue. After identifying the problems with implementing variable swapping (the core operation in dynamic reordering) in breadth-first based packages, the authors propose techniques to handle the computational and memory overheads. They feel that combining dynamic reordering with the powerful manipulation algorithms of a breadth-first based scheme can significantly enhance the performance of BDD based algorithms. The efficiency of the proposed techniques is demonstrated on a range of examples.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A universal Pezaris array multiplier generator for SRAM-based FPGAs 用于基于sram的fpga的通用Pezaris阵列乘法器
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628913
Jörn Stohmann, E. Barke
{"title":"A universal Pezaris array multiplier generator for SRAM-based FPGAs","authors":"Jörn Stohmann, E. Barke","doi":"10.1109/ICCD.1997.628913","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628913","url":null,"abstract":"A new approach to implement fast array multipliers of any word length in SRAM-based FPGAs is presented. The proposed method is based on a generic FPGA model and, therefore, suitable for most commercial FPGA devices. Taking the logical structure of the multiplier into account, technology mapping including adaptive structure generation as well as signal flow driven placement and automatic partitioning are efficiently performed yielding implementations of higher performance and better resource utilization than previously published.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Power compiler: a gate-level power optimization and synthesis system 功率编译器:一个门级功率优化与综合系统
Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628852
Benjamin Chen, I. Nedelchev
{"title":"Power compiler: a gate-level power optimization and synthesis system","authors":"Benjamin Chen, I. Nedelchev","doi":"10.1109/ICCD.1997.628852","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628852","url":null,"abstract":"Commercial synthesis tools traditionally perform timing and area optimization, however power reduction is rapidly becoming an equally important design goal. Recent research in power optimization has produced several algorithms, however, each algorithm is focused on one aspect of the whole power equation. This paper describes a commercial tool capable of optimizing power at the gate-level in addition to performing area and timing optimization. A power analysis engine that models all aspects of power consumption is integrated into the optimization tool so that all aspects of power are considered. Experimental results show an average 11.46% reduction on industrial circuits with a peak reduction of 66.62%. All delay constraints are met and an average 9.41% increase in area is observed.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127874038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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