Alpha 21264微处理器总线接口单元的正式实现验证

G. Bischoff, K. Brace, Samir Jain, R. Razdan
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引用次数: 18

摘要

本文提出了Alpha 21264微处理器总线接口单元(BIU)晶体管实现的形式化验证方法。我们比较了从寄存器传输电平(RTL)编译的逻辑描述与从定制设计的晶体管级原理图中提取的逻辑描述。BOVE,我们基于bdd的验证工具,不需要锁存器对锁存器的对应,因此允许RTL在设计过程中更加稳定,并使原理图设计者可以自由地实现竞争和时序优化。一个独特的“重新计时”比较算法有效地比较分区,包括多个管道阶段,重新计时优化和预充电逻辑。BOVE还验证在RTL和原理图中具有不同状态编码的小型有限状态机。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor
In this paper we present our method of formal verification of the transistor implementation of the Bus Interface Unit (BIU) of the Alpha 21264 microprocessor. We compare the logical description compiled from the Register Transfer Level (RTL) against that extracted from the custom-designed transistor-level schematics. BOVE, our BDD-based verification tool, does not require latch-to-latch correspondence, thus allowing the RTL to be more stable during the design process and giving the schematic designers freedom to implement race and timing optimizations. A unique "retiming" comparison algorithm efficiently compares partitions that include multiple pipeline stages, retiming optimizations and precharge logic. BOVE also verifies small finite-state machines that have different state encodings in the RTL and schematic.
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