Power compiler: a gate-level power optimization and synthesis system

Benjamin Chen, I. Nedelchev
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引用次数: 28

Abstract

Commercial synthesis tools traditionally perform timing and area optimization, however power reduction is rapidly becoming an equally important design goal. Recent research in power optimization has produced several algorithms, however, each algorithm is focused on one aspect of the whole power equation. This paper describes a commercial tool capable of optimizing power at the gate-level in addition to performing area and timing optimization. A power analysis engine that models all aspects of power consumption is integrated into the optimization tool so that all aspects of power are considered. Experimental results show an average 11.46% reduction on industrial circuits with a peak reduction of 66.62%. All delay constraints are met and an average 9.41% increase in area is observed.
功率编译器:一个门级功率优化与综合系统
商业合成工具传统上执行时序和面积优化,但功耗降低正迅速成为一个同样重要的设计目标。近年来在功率优化方面的研究产生了几种算法,然而,每种算法都集中在整个功率方程的一个方面。本文描述了一种能够在栅极级优化功率以及进行面积和时序优化的商用工具。在优化工具中集成了一个功率分析引擎,对功耗的各个方面进行建模,以便考虑功率的各个方面。实验结果表明,在工业电路中平均降低11.46%,峰值降低66.62%。所有延迟限制都得到满足,并且观察到面积平均增加了9.41%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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