Design and implementation of low-power digit-serial multipliers

Abstract

Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel design methodology is presented which permits bit-level pipelining of the digit-serial architectures. This achieves sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for transformed multipliers with smaller digit-sizes (/spl les/4), the singly-redundant multiplier consumes the least power and for larger digit sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/(2 W), where W represents the word-length. The proposed digit-serial multipliers consume on an average 20% lower power than the traditional digit-serial architectures for the non-pipelined case, and about 5-15 times lower power for the bit-level pipelined case. Also, modified Booth (1951) recoding is applied to transformed multipliers and it is found that the recoded multipliers consume about 22% lower power than the transformed multipliers without recoding.