Synthesis of delay verifiable sequential circuits using partial enhanced scan

Abstract

The path delay fault testability of sequential circuits is limited by state transitions that can be produced during normal operation. As a result, there may be untestable faults some of which may affect circuit behavior. The authors first extend the concept of primitive faults to sequential circuits. They then describe a method of selecting a set of flip-flops for partial enhanced-scan, such that falling transitions on all paths are made robustly testable in a two-level prime and irredundant realization of the sequential circuit. It results in a robust or VNR test for every rising transition primitive fault, using the available state transitions. A method of synthesizing sequential circuits such that untestable faults do not affect the initialization, is presented. An area comparison between area-optimized and delay-verifiable versions of the MCNC '91 benchmark circuits is also presented.