N. Dutt, S. Malik, L. Augusteijn, B. Fu, A. Nicolau, C. Polychronopoulos
{"title":"If software is king for systems-on-silicon, what's new in compilers?","authors":"N. Dutt, S. Malik, L. Augusteijn, B. Fu, A. Nicolau, C. Polychronopoulos","doi":"10.1109/ICCD.1997.628889","DOIUrl":null,"url":null,"abstract":"While software is already a significant component in today's system-on-silicon, it is expected to greatly dominate future generations of systems-on-silicon that will contain several (possibly heterogeneous) programmable processors, as well as reconfigurable hardware blocks and large amounts of on-chip memory. In this context, one could argue that the problems for compiler designers haven't changed at all, since the basic issues all boil down to the traditional challenges of: 1) coarse-grain parallelism extraction for the multiple processors on chip, 2) instruction level parallelism exploitation for individual processors, and 3) retargetable code generation for versions of the on-chip processors. This paper summarizes the positions of the panelists who presented their views on the new challenges in compilers for future systems-on-silicon, and who debated these issues at ICCD '97.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1997.628889","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
While software is already a significant component in today's system-on-silicon, it is expected to greatly dominate future generations of systems-on-silicon that will contain several (possibly heterogeneous) programmable processors, as well as reconfigurable hardware blocks and large amounts of on-chip memory. In this context, one could argue that the problems for compiler designers haven't changed at all, since the basic issues all boil down to the traditional challenges of: 1) coarse-grain parallelism extraction for the multiple processors on chip, 2) instruction level parallelism exploitation for individual processors, and 3) retargetable code generation for versions of the on-chip processors. This paper summarizes the positions of the panelists who presented their views on the new challenges in compilers for future systems-on-silicon, and who debated these issues at ICCD '97.