{"title":"深亚微米MOSFET电路的新型仿真","authors":"S. Bruma, R. Otten","doi":"10.1109/ICCD.1997.628850","DOIUrl":null,"url":null,"abstract":"The effects of scaling down the MOSFET dimensions to the deep-submicron range lead to operating regions that may be modeled by locally linear equations. The piecewise linear simulator seems to be the obvious choice. Certain requirements must be satisfied by a PL simulator for the successful manipulation of the proposed MOSFET model. Simulation results demonstrate the efficiency in simulating large deep-submicron MOSFET circuits. Several levels of hierarchy can be simulated due to the uniform PL modeling technique.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Novel simulation of deep-submicron MOSFET circuits\",\"authors\":\"S. Bruma, R. Otten\",\"doi\":\"10.1109/ICCD.1997.628850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The effects of scaling down the MOSFET dimensions to the deep-submicron range lead to operating regions that may be modeled by locally linear equations. The piecewise linear simulator seems to be the obvious choice. Certain requirements must be satisfied by a PL simulator for the successful manipulation of the proposed MOSFET model. Simulation results demonstrate the efficiency in simulating large deep-submicron MOSFET circuits. Several levels of hierarchy can be simulated due to the uniform PL modeling technique.\",\"PeriodicalId\":154864,\"journal\":{\"name\":\"Proceedings International Conference on Computer Design VLSI in Computers and Processors\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Conference on Computer Design VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1997.628850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1997.628850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel simulation of deep-submicron MOSFET circuits
The effects of scaling down the MOSFET dimensions to the deep-submicron range lead to operating regions that may be modeled by locally linear equations. The piecewise linear simulator seems to be the obvious choice. Certain requirements must be satisfied by a PL simulator for the successful manipulation of the proposed MOSFET model. Simulation results demonstrate the efficiency in simulating large deep-submicron MOSFET circuits. Several levels of hierarchy can be simulated due to the uniform PL modeling technique.