Proceedings International Conference on Computer Design VLSI in Computers and Processors最新文献_第8页

Fast cache access with full-map block directory 快速缓存访问与全映射块目录

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628924

J. Peir, W. Hsu

引用次数: 2

A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar hp -凸样例的层次网络结构的比较评价

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628877

R. Castañeda, Xiaodong Zhang, James M. Hoover

{"title":"A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar","authors":"R. Castañeda, Xiaodong Zhang, James M. Hoover","doi":"10.1109/ICCD.1997.628877","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628877","url":null,"abstract":"The Convex Exemplar (SPP1000 and SPP2000 series) is a new commercial distributed shared-memory architecture. Using a set of system kernels and two application programs, we examine performance effects on network latency, hot spot contention, cache coherence and overall scaling capability, which result both from the choice of the network structure as well as from its CC-NUMA memory system feature. Since the KSR-1 was also targeted at scalable cache coherent shared-memory systems by using hierarchical interconnection networks, we compared the architecture and performance results with the KSR-1. Our experiments indicate that the memory access latency of the Exemplar is comparatively low due to its fast processor node and the unique network/system structure. In addition, the Coherent Toroidal Interconnect (CTI) rings are efficient in handling cache coherence activities on the Exemplar. However, the Exemplar synchronization primitives need further exploit its hierarchical architecture in a high contention environment. As we expect with extremely fast processors in a hierarchical memory structure, the high-speed cluster-based Exemplar system is more sensitive to data locality.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design methodology for the high-performance G4 S/390 microprocessor 高性能g4s /390微处理器的设计方法

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628873

K. Shepard, S. Carey, D. Beece, R. F. Hatch, G. Northrop

引用次数: 2

Multi-column implementations for cache associativity 缓存关联的多列实现

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628915

Chenxi Zhang, Xiaodong Zhang, Yong Yan

引用次数: 8

Checking formal specifications under simulation 检查模拟下的正式规范

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628908

William Canfield, E. Emerson, A. Saha

引用次数: 20

Power constrained design of multiprocessor interconnection networks 多处理器互连网络的功耗约束设计

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628902

C. Patel, S. Chai, S. Yalamanchili, D. Schimmel

引用次数: 89

Circuit-based description and modeling of electromagnetic noise effects in packaged low-power electronics 封装低功率电子器件中电磁噪声效应的电路描述与建模

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628860

A. Cangellaris, W. Pinello, A. Ruehli

引用次数: 2

Design and test: The Lost World 设计和测试:失落的世界

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628890

W. Joyner

引用次数: 0

Formal verification of the HAL S1 System cache coherence protocol HAL S1系统缓存一致性协议的正式验证

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628906

A. Hu, M. Fujita, Chris Wilson

{"title":"Formal verification of the HAL S1 System cache coherence protocol","authors":"A. Hu, M. Fujita, Chris Wilson","doi":"10.1109/ICCD.1997.628906","DOIUrl":"https://doi.org/10.1109/ICCD.1997.628906","url":null,"abstract":"The paper describes the authors' experience applying formal verification to the cache coherence protocol of the HAL S1 System, a shared-memory and/or message-passing multiprocessor consisting of standard Intel Pentium/sup (R/) Pro symmetric multiprocessing (SMP) servers connected by HAL's proprietary Mercury Interconnect to create a cache-coherent, non-uniform memory access (CC-NUMA) machine. In recent years, several researchers have described the verification of cache coherence protocols to demonstrate the potential of formal verification. In this project, they sought to quantify this potential by carefully tracking the effort and results of applying formal verification, rather than simply demonstrating that verification was possible. Based on their records and experience, they show that protocol-level formal verification, properly applied, is sufficiently well-understood to be routinely undertaken, and they describe the techniques used to simplify the verification process. On the negative side, their formal verification methodology has limitations, so they outline the pitfalls encountered and recommend ways to minimize them.","PeriodicalId":154864,"journal":{"name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120976030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Improving design turnaround time via two-levels HW/SW co-simulation 通过两级硬件/软件联合仿真提高设计周转时间

Proceedings International Conference on Computer Design VLSI in Computers and Processors Pub Date : 1997-10-12 DOI: 10.1109/ICCD.1997.628901

A. Allara, S. Filipponi, W. Fornaciari, F. Salice, D. Sciuto

引用次数: 0