Improving design turnaround time via two-levels HW/SW co-simulation

Abstract

The steadily growing demand of fast turnaround time will shift system tuning from physical prototyping to virtual prototyping. The paper proposes a novel approach for mixed HW-SW implementation of embedded systems, allowing high-level simulation of the overall architecture as well as a deeper analysis of timing performance by exploiting commercial VHDL CAD tools. At the higher level, functional debugging and tradeoff analysis is performed on an OCCAM-based system-level model and at the lower level a VHDL-based description for both the HW and SW is built for fine grain verification of the system. The paper introduces the two levels of simulation, showing their impact in terms of design flow management and design time.