A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar

Abstract

The Convex Exemplar (SPP1000 and SPP2000 series) is a new commercial distributed shared-memory architecture. Using a set of system kernels and two application programs, we examine performance effects on network latency, hot spot contention, cache coherence and overall scaling capability, which result both from the choice of the network structure as well as from its CC-NUMA memory system feature. Since the KSR-1 was also targeted at scalable cache coherent shared-memory systems by using hierarchical interconnection networks, we compared the architecture and performance results with the KSR-1. Our experiments indicate that the memory access latency of the Exemplar is comparatively low due to its fast processor node and the unique network/system structure. In addition, the Coherent Toroidal Interconnect (CTI) rings are efficient in handling cache coherence activities on the Exemplar. However, the Exemplar synchronization primitives need further exploit its hierarchical architecture in a high contention environment. As we expect with extremely fast processors in a hierarchical memory structure, the high-speed cluster-based Exemplar system is more sensitive to data locality.