Electronics Manufacturing Issues最新文献

Process Characterization and the Effect of Process Defects on Flip Chip Reliability 制程表征及制程缺陷对倒装晶片可靠性的影响

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0916

B. Lewis, Hilary Sasso

{"title":"Process Characterization and the Effect of Process Defects on Flip Chip Reliability","authors":"B. Lewis, Hilary Sasso","doi":"10.1115/imece1999-0916","DOIUrl":"https://doi.org/10.1115/imece1999-0916","url":null,"abstract":"\u0000 Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process?\u0000 The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117176736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

In-Situ Warpage Measurement During Thermal Cycling of Dielectric Coated SS Substrate for Large Area MCM-D Packaging 大面积MCM-D封装介质涂层SS基板热循环过程中的原位翘曲测量

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0930

Anh X. Dang, I. C. Ume, S. Bhattacharya

引用次数: 0

High-Resolution Wafer Surface Topology Measurement Using Phase-Shifting Shadow Moiré Technique 基于相移阴影成像技术的高分辨率晶圆表面拓扑测量

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0912

S. Wei, E. Guan, I. Kao, F. Chiang

{"title":"High-Resolution Wafer Surface Topology Measurement Using Phase-Shifting Shadow Moiré Technique","authors":"S. Wei, E. Guan, I. Kao, F. Chiang","doi":"10.1115/imece1999-0912","DOIUrl":"https://doi.org/10.1115/imece1999-0912","url":null,"abstract":"\u0000 The traditional shadow moiré technique has been employed, using the fringe pattern information and numerical interpolation, to construct the wafer surface topology. In this paper, phase-shifting shadow moiré technique is discussed and applied to the measurement of wafer surface topology with high resolution. The phase-shifting technique takes advantage of the gray level information to increase the physical resolution of the measurement. A series of fringe patterns are recorded while they are shifted by moving the wafer along the direction perpendicular to wafer surface. The phase is encoded in the variations in the intensity pattern of the recorded fringe images, and a simple point-by-point calculation recovers the phase. The needs to locate the fringe centers and interpolation are eliminated. Since the depth variation of wafer surface is very small, usually within the range of 0.1 to 20 microns, very fine grating is required in order to capture the small depth variation. However, very fine grating will introduce strong diffraction effect which blurs the fringe patterns. In this study, the Talbot distance is applied to obtain images with good contrast. The phase shift is realized by moving the wafer to change the distance between the wafer surface and the reference grating. A four-step phase wrapping algorithm is used to calculate the phase. The phase pattern recovered from four fringes patterns is presented. Future work such as how to reduce the noise, how to do phase unwrapping and calibration is also discussed.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129835729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of Volume on Ceramic Ball-Grid Array Solder Life 体积对陶瓷球栅阵列焊料寿命的影响

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0929

S. McKeown, C. Sahay

引用次数: 0

Constitutive and Cyclic Damage Model of 63Sn-37Pb Solder 63Sn-37Pb焊料本构及循环损伤模型

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/1.1407825

V. Stolkarts, L. Keer, M. Fine

引用次数: 20

An Integrated Model for Electromagnetic Field and Heat Transfer in a Cylindrical Silicon Tube Growth System 圆柱形硅管生长系统中电磁场与传热的集成模型

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0911

A. Roy, Q.-S. Chen, H. Zhang, V. Prasad

引用次数: 0

Artwork Scaling Factor for Inner Layers in Multi-Layer Board Manufacture 多层板制造中内层工艺尺寸的比例系数

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0919

O. Christofferson, C. Sahay

引用次数: 0

A Model of Crack Nucleation in Layered Electronic Assemblies Under Thermal Cycling 热循环作用下层状电子组件裂纹成核模型

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/1.1286100

A. Chandra, Yonggang Huang, Z. Q. Jiang, K. Hu, G. Fu

{"title":"A Model of Crack Nucleation in Layered Electronic Assemblies Under Thermal Cycling","authors":"A. Chandra, Yonggang Huang, Z. Q. Jiang, K. Hu, G. Fu","doi":"10.1115/1.1286100","DOIUrl":"https://doi.org/10.1115/1.1286100","url":null,"abstract":"\u0000 A model for crack nucleation in layered electronic assemblies under thermal cycling is developed in this paper. The present model includes three scales: (i) at the microscale or the mechanism level, the damage mechanisms such as diffusive void growth or fatigue cracks, determine the damage growth rate; (2) at an intermediate mesoscale, the localized damage bands are modeled as variable stiffness springs connecting undamaged materials; and (iii) at the macroscale or the continuum level, the localized damage band growing in an otherwise undamaged material is modeled as an array of dislocations. The three scales are then combined together to incorporate damage mechanisms into continuum analysis. Traditional fracture mechanics provides a crack propagation model based on pre-existing cracks. The present work provides an approach for predicting crack nucleation. The proposed model is then utilized to investigate crack nucleations in three-layered electronic assemblies under thermal cycling. The damage is observed to accumulate rapidly in the weakest regions of the band. Estimates are obtained for critical time or critical number of cycles at which a macroscopic crack will nucleate in these assemblies under thermal cycling. This critical number of cycles is found to be insensitive to the size of the damage cluster, but decreases rapidly as the local excess damage increases.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130227962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Design and Implementation of a Flexible Intelligent Electronics Remanufacturing System 柔性智能电子再制造系统的设计与实现

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0921

I. Fidan, R. Kraft, S. Derby

{"title":"Design and Implementation of a Flexible Intelligent Electronics Remanufacturing System","authors":"I. Fidan, R. Kraft, S. Derby","doi":"10.1115/imece1999-0921","DOIUrl":"https://doi.org/10.1115/imece1999-0921","url":null,"abstract":"\u0000 Electronic manufacturing of circuit boards has undergone major changes in the last decade as new technologies have emerged and are perfected to replace older ones. A result of the increased board layout densities and higher levels of integration at the chip level is a dramatic increase in the value of circuit boards. The benefit is much more functionality in smaller boards, but the disadvantage is significant losses when a defective board must be scrapped. The same technology that has increased the density of the board functionality has made manual rework to correct manufacturing defects almost impossible. Higher levels of circuit integration in moving from VLSI to ULSI (Ultra Large Scale Integration) have required more pin-outs on the packages which in turn has resulted in finer lead pitches and a change from through-hole mounting to surface mounting technology (SMT). These two changes, with the decreased interchip spacing, have necessitated the use of automation to perform reliable component replacement on defective boards. This paper discusses the complexities of integrating several automation technologies into a single robotic electronic remanufacturing workcell. Involved are vision guidance, control software development, and multiple special end-effector designs for the several required steps, including defective component removal, board cleaning, solder paste dispensing, component placement, and laser soldering [1].","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"7 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132579857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance of Thermal Enhancements in Chip on Flex Flex芯片的热增强性能

Electronics Manufacturing Issues Pub Date : 1999-11-14 DOI: 10.1115/imece1999-0923

Gary Miller, C. Sahay

引用次数: 0