Artwork Scaling Factor for Inner Layers in Multi-Layer Board Manufacture

Abstract

Demands for high-density multi-layer printed circuits continue to push the limits of common materials and process capabilities. Materials and processes that can improve current manufacturing tolerances will improve yields on current designs as well as free up printed circuit board real estate for increased circuit densities. Achieving these improvements requires an understanding of all the variables that contribute to inner layer feature-to-drilled hole registration and how tolerances stack up to an overall capability. These variables include both material types and process parameters. This paper discusses the variables that affect overall registration capabilities, presents a technique for predicting artwork scaling factors.