Electronics Manufacturing Issues最新文献

{"title":"Interaction Between Wire and Ingot in Wiresaw Slicing","authors":"Fuqian Yang, J. C. Li, I. Kao","doi":"10.1115/imece1999-0910","DOIUrl":"https://doi.org/10.1115/imece1999-0910","url":null,"abstract":"\u0000 The deformation of the wire in the wiresaw slicing process was studied by considering directly the mechanical interaction between the wire and the ingot. The wire tension on the upstream is larger than on the downstream due to the friction force between the wire and the ingot. The tension difference across the cutting zone increases with friction and the span of the contact zone. The pressure in the contact zone increases from the entrance to the exit if the wire bending stiffness is ignored. The finite element results show that the wire bending stiffness plays an important role in the wire deformation. Higher wire bending stiffness (larger wire size) generates higher force acting onto the ingot for the same amount of wire deformation, which will leads to higher material removal rate and kerf loss. While larger wire span will reduce the force acting onto the ingot for a given ingot displacement in the direction perpendicular to the wire.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121577236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Analysis of Flip Chip on Board Assemblies Using No-Flow Underfill Materials","authors":"R. Thorpe, D. Baldwin","doi":"10.1115/imece1999-0914","DOIUrl":"https://doi.org/10.1115/imece1999-0914","url":null,"abstract":"\u0000 As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity and reliability assessment is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to evaluate the reliability of no-flow underfill materials. The reliability performance of four underfill materials is evaluated using six test vehicles. Accelerated reliability tests performed on the test vehicles included liquid/liquid and air/air thermal cycling, autoclave, and J-STD-020 Level 3 preconditioning. No-flow underfill materials tested in this work have demonstrated the ability to survive in excess of 1000 cycles of liquid/liquid thermal shock, survive more than 100 hours of autoclave, and pass J-STD-020 Level 3 preconditioning.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125655547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fundamental Analyses of Smart Tooling for Assembly of Thin Flexible Circuit and Board Systems","authors":"Ruijun Chen, D. Baldwin","doi":"10.1115/imece1999-0917","DOIUrl":"https://doi.org/10.1115/imece1999-0917","url":null,"abstract":"\u0000 Flexible nature of flexible circuits/boards poses new fixture tooling challenges for standard surface mount assembly equipment. The flexible substrates experience significant transverse displacements under perpendicular assembly forces during solder paste printing and component placement processes. The displacements result in misregistration of the component leads and substrate bond pads, leading to assembly process defects. Solder reflow process further complicates the issue due to the thermo-mechanical warpage induced. Reengineered and specialized dedicated tooling for fixturing flexible substrates in standard assembly equipment is becoming extremely important. This paper focuses on developing analysis methodologies and theories for implementing Smart Tooling. The primary goals being to determine the impact of fixturing on assembly process quality and to determine optimum fixturing configurations for thin flexible circuit board assemblies based on circuit board design data. A mathematical model to describe both transverse and perpendicular displacements of flex substrates is developed, and its close-form solution for transverse displacements is obtained. Using a “near” optimum fixturing configuration to minimize transverse displacements is verified.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134620047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of On-Die Discrete Heating on Thermal Performance Characteristics of Silicon Based IC Electronic Packages","authors":"V. H. Adams, K. Ramakrishna","doi":"10.1115/imece1999-0922","DOIUrl":"https://doi.org/10.1115/imece1999-0922","url":null,"abstract":"\u0000 Simulations for thermal characterization of electronic packages for silicon-based integrated circuit (IC) components typically assume one of the two uniform heat generation conditions. They are: (1) an isoflux condition in which heat generation is uniformly distributed over the active surface of the die, or (2) a uniform heat generation over the entire (or active) volume of the die. The use of these models may be justified due to high thermal conductivity of silicon, size of the devices on the die, and their relatively uniform spatial distribution over the entire surface of the die in the traditional silicon technologies. However, the current and future technologies are migrating towards embedded systems solutions, such as system-on-chip, and in traditional applications devices are brought in close proximity to each other for improved on-chip electrical performance. These trends result in localized regions of power dissipation on the die that would invalidate the use of traditional uniform generation models in the thermal characterization.\u0000 The present study examines the effect of discrete heat sources (as opposed to uniformly distributed sources) on the die on thermal performance and characterization of the electronic packages. For this purpose, a conjugate heat transfer problem of a memory chip in a 119 I/O flip chip ceramic and plastic ball grid array (FC-C & PBGA) package under natural and forced convection conditions. First the model is validated against experimentally measured thermal data on a 119 I/O FC-C & P BGA daisy-chain test packages with a thermal test die with uniformly distributed resistive heat source. Junction-to-ambient temperature difference predictions from the simulations are within 10% of the measurements for the uniform heating case. The validated model is then suitably modified to account for discrete heat sources and actual substrates. Results from the discrete heat sources study show a 15–20% increase in predicted junction-to-ambient temperature difference and a larger (a 10–15 °C) temperature variation across the active face of the die than for with a uniform heat source. These results call for the use of discrete heat sources in the thermal characterization of new generation of embedded silicon technologies. They also point to the need for development of test die and characterization methodologies for these technologies with discrete heat sources.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127530830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Performance & Manufacturability Evaluation of Bump Chip Carrier Packages","authors":"L. Mercado, V. Sarihan, R. Fiorenzo","doi":"10.1115/imece1999-0918","DOIUrl":"https://doi.org/10.1115/imece1999-0918","url":null,"abstract":"\u0000 Bump Chip Carrier® (BCC) is an attractive solution to the demand of high packaging density of low I/O-count packages. It offers low cost, high performance, and much smaller package size than Quad Flat Packages (QFP). Electrically, BCC offers significant performance advantage as a function of frequency. It also has customizable configurations. In this paper, an extensive finite element thermomechanical analysis has been conducted to evaluate the reliability of BCC packages during thermal cycling. The effect of a variety of parameters on package reliability was evaluated, including board thickness, package size mold material, solder paste thickness, and terminal height. The solder reliability of corner leads vs. inner leads, as well as square leads vs. rectangular leads was also investigated. Then some manufacturing issues were studied. During manufacturing, molded panels for BCC packages are undergoing significant warpage. Two types of mold designs were compared through 3D finite element analysis. A variety of mold compound materials were evaluated. The most effective way to reduce warpage was suggested.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127553638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Computational Model for Free Abrasive Machining of Brittle Silicon Using a Wiresaw","authors":"M. Bhagavat, I. Kao","doi":"10.1115/imece1999-0913","DOIUrl":"https://doi.org/10.1115/imece1999-0913","url":null,"abstract":"\u0000 The present paper deals with physics based computational modeling of the wiresaw Free Abrasive Machining (FAM). The wiresaw is used to slice large diameter wafers of predominantly brittle semi-conductors such as silicon. The wiresawing model proposed in the present paper involves cutting action by ‘floating’ abrasives. It is proposed that the abrasive carrying slurry forms a film in the cutting zone by an elasto-hydrodynamic action. Finite Element Analysis shows this film to be in general thicker than the average abrasive size. This signifies a ‘float’ machining condition, wherein there is no direct pressing of abrasives by the wire. Typical rolling and indenting of abrasives under such free body abrasion environment is supported by hydrodynamic shear and pressure respectively. The abrasive is assumed to remove material by typical indentation fracture. Finite element analysis of stresses underneath an indenting abrasive shows that cracks leading to chipping occur only during unloading of indented abrasives (during rolling). The volume of the chip removed in a single indentation is proportional to the volume of plastic zone underneath the indenter. We integrate the elasto-hydrodynamic model and the single abrasive indentation model into a complete representative model of wiresawing.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Issues That Arise due to Manufacturing Processes: Evaluation and Measurement Techniques","authors":"B. Sammakia, S. Sathe","doi":"10.1115/imece1999-0925","DOIUrl":"https://doi.org/10.1115/imece1999-0925","url":null,"abstract":"\u0000 This paper describes the methodology used to design and evaluate the strength and reliability of the thermal interface between the chip and heat sink (coverplate) in a TBGA first level package. TBGA is a new technology that is part of the new generation of organic ball grid array chip carriers that are quickly gaining popularity for packaging various microprocessors and memory in portables, desktops, mid-range and high-end mainframes. The package consists of a Kapton or Upilex dielectric layer with one signal plane and one ground plane on either side, as shown in Figure 1. The chip is attached to the package with the signal side ‘down’, that is, facing the card. This leaves the backside of the chip available for coverplate (flat copper heat sink) attach. This direct access to the chip allows for a very effective thermal path from the chip directly to the heat sink, resulting in outstanding thermal performance. It is therefore essential to ensure that the interface between the chip and the heat sink remains intact through the end of the assembly processes for the package, including second-level attach to the board and rework. The interface must also remain intact through the life of the product. It is also necessary to ensure that the interface survives all of the necessary qualification stresses including accelerated thermal cycling, thermal age and deep thermal cycling, to name a few. First the results of a numerical analysis are presented showing the impact of surface de-lamination upon the thermal performance of the package. The model used is a full three-dimensional conjugate model accounting for conduction and radiation effects in the package, as well as the natural convection flow in the surrounding air. The results confirm that delamination of the interface degrades the thermal performance of the package. The model and test results also indicate that, due to the robustness of the package, voids or incomplete coverage of the chip with the thermal adhesive results in a relatively small degradation of the thermal performance of the package, provided total de-lamination of the chip or coverplate does not occur. The methodology used in evaluating different design options, such as adhesive material and heat sink surface treatment, is then described in detail. The primary method used for evaluating interfacial strength is a modified fracture toughness test (MFTT). This is the best measure of resistance to crack propagation. In conjunction with the MFTT, a sonographic technique was used to evaluate the integrity of the interface as a function of stress. Finally, a laser moiré tool is employed to evaluate the strains in the package due to thermal stress. The moiré results are shown for an intact package as well as for a completely de-laminated package, showing the differences in the mechanical response of the package due to delamination.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116808316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Study of the Aperture Filling Process in Solder Paste Stencil Printing","authors":"Jianbiao Pan, G. Tonkay","doi":"10.1115/imece1999-0920","DOIUrl":"https://doi.org/10.1115/imece1999-0920","url":null,"abstract":"\u0000 Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"57 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated Transient Thermal and Mechanical Analysis of Molded PBGA Packages During Thermal Shock","authors":"L. Mercado, T. Lee, J. Cook","doi":"10.1109/6040.909627","DOIUrl":"https://doi.org/10.1109/6040.909627","url":null,"abstract":"\u0000 During thermal shock, large thermal gradients exist within a molded plastic ball grid array (PBGA) package. The conventional assumption of uniform temperature distribution becomes invalid. In this paper, an integrated thermal-mechanical analysis was performed to evaluate the transient effect of thermal shock. For comparison, an isothermal analysis was also conducted. The computational fluid dynamics (CFD) method was used to obtain the thermal boundary conditions surrounding the package. The heat transfer coefficient obtained through CFD was compared to two analytical solutions. It was found that the analytical values were not acceptable in the time period of interest. Therefore, to obtain the actual maximum die stress, CFD solution has to be used instead of analytical solutions to derive the thermal boundary condition. This boundary condition was then applied to the package and a sequentially coupled heat transfer and thermal stress analysis was performed. The transient analysis has shown that high stresses occur in the die due to thermal shock, which can not be seen under the traditional isothermal assumption. The impact of PBGA package parameters on transient die stress was also studied, including mold thickness and substrate thickness. The results in this paper could be applied to either wire bond or flip-chip PBGA packages.","PeriodicalId":153178,"journal":{"name":"Electronics Manufacturing Issues","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115567072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}