1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)最新文献_第5页

Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems 51.84 Mb/s超高速数字用户环路(VDSL)调制解调器的低功耗均衡器

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715794

M. Goel, Naresh R Shanbhag

引用次数: 21

Blind channel and symbol estimation for wireless communications via an affinity neural network 基于亲和神经网络的无线通信盲信道和符号估计

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715801

R. Hernandez, V. Jain

引用次数: 0

A performance evaluation of a RISC-based digital signal processor architecture 基于risc的数字信号处理器体系结构的性能评估

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715816

Jiyang Kang, Jong Jin Lee, Wonyong Sung

引用次数: 3

A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs 一个核心生成器，用于片上系统设计的完全可合成和高度可参数化的risc内核

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715818

Mladen Berekovic, D. Heistermann, P. Pirsch

{"title":"A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs","authors":"Mladen Berekovic, D. Heistermann, P. Pirsch","doi":"10.1109/SIPS.1998.715818","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715818","url":null,"abstract":"Driven by the rapid advances in semiconductor technology the number of functional units that can be implemented on a single chip is rapidly increasing. This raises the need for programmable but small processor cores to handle control of operation as well as communication and synchronization between the different functional modules on the chip. We have developed a soft core generator for highly parameterizable RISC-cores. The instruction word width can be arbitrarily chosen between 8 and 32 bits. Independent of this, the data-path width can be selected between 8 and 64 bits respectively. DSP-like performance can be achieved with the instantiation of a 64-bit (splittable-) MAC-unit in the data-path. The number of registers is arbitrarily scalable. The resulting cores are generated in RTL-VHDL and are fully synthesizable. Worst-case timing simulation shows 100 MHz achievable clock-speed using a 3LM 0.5 /spl mu/m standard-cell technology. The size of the synthesized cores ranges from 900 gates for a multi-cycle 8 bit core to 10k gates for a 5-stage pipelined 32 bit core with 8 registers. Interfaces and behavioral models are provided for instruction and data memories as well as a runnable VHDL testbench with basic test patterns. As a result, a 16 bit RISC core with instruction and data memories can be implemented on 1 mm/sup 2/ of silicon area in a 0.35 /spl mu/m technology.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127473194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Input recoding for reducing power in distributed arithmetic 分布式算法中用于降低功率的输入重编码

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715823

J. Sacha, M. J. Irwin

引用次数: 4

Re-evaluating MPEG motion compensation search criteria 重新评估MPEG运动补偿搜索标准

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715775

B. Bishop, T. Kelliher, R. Owens, M. J. Irwin

引用次数: 2

High-speed VLSI state-space orthogonal IIR digital filters using matrix lookahead 高速VLSI状态空间正交IIR数字滤波器采用矩阵前馈

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715804

J. Ma, K. K. Parhi

{"title":"High-speed VLSI state-space orthogonal IIR digital filters using matrix lookahead","authors":"J. Ma, K. K. Parhi","doi":"10.1109/SIPS.1998.715804","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715804","url":null,"abstract":"The increasing demands for multimedia and wireless communication applications have had much impact on design of high-speed and low-power modern DSP systems. Orthogonal IIR digital filters can achieve a sharp transition band and have good finite word-length behavior and are used in many modern DSP applications such as mobile communications. However, Cordic-based fine-grain pipelined true orthogonal IIR digital filters have not been developed so far. A state-space-based novel algorithm for designing fine-grain pipelined true orthogonal IIR digital filters is proposed using the matrix lookahead technique. The algorithm only involves applying orthogonal transformations that are known to be numerically very reliable, and therefore is ideal for VLSI implementations. The proposed filter architecture can be operated at arbitrarily high sample rates and achieves linear increase in hardware complexity with respect to the filter order and pipelining level. It consists of only Givens rotations which can be mapped onto Cordic arithmetic-based processors. Finally, an intermediate frequency filter for the USA mobile telephone system is designed using the proposed orthogonal filter synthesis algorithm.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130802985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A system-level reuse methodology for embedded data-dominated applications 用于嵌入式数据主导应用程序的系统级重用方法

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715817

F. Vermeulen, F. Catthoor, D. Verkest, H. de Man

引用次数: 4

A uniform analysis method for DSP architectures and instruction sets with a comprehensive example 一种DSP体系结构和指令集的统一分析方法，并附综合实例

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715815

R. Owen, D. Martin

{"title":"A uniform analysis method for DSP architectures and instruction sets with a comprehensive example","authors":"R. Owen, D. Martin","doi":"10.1109/SIPS.1998.715815","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715815","url":null,"abstract":"As digital signal processing finds broader areas of application, more processors are adapting to the need for DSP operations. MMX instructions have been added to the Pentium, high-performance RISC have done similar things for workstations, and microcontrollers are doing it for embedded applications. Digital signal processors too are changing as there are increased demands for higher performance. With new processors having such vastly different architectures and employing different processing strategies, it is increasingly difficult to make meaningful DSP performance comparisons between them. This paper reviews the normal representations or views of a processor: hardware architecture, programming model, instruction set architecture and benchmarks, and their role in DSP performance estimation in four critical areas. A uniform model is proposed for the first three views, which includes a new annotated form of programming model using signal-flow-graph-like techniques. Finally, one of the new types of processors, the Siemens TriCore Microcontroller-DSP, is analyzed to test and illustrate the new models and methodology.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Multi-channel reverberation for computer music applications 多通道混响的计算机音乐应用

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715784

D. Murphy, D. Howard, A. Tyrrell

引用次数: 4