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1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)最新文献

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A portable system for high-resolution digital image acquisition using wavelet image compression 基于小波图像压缩的便携式高分辨率数字图像采集系统
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715776
U. Schelinski, S. Danz, K. Frommhagen, M. Scholles, M. Schwarzenberg
{"title":"A portable system for high-resolution digital image acquisition using wavelet image compression","authors":"U. Schelinski, S. Danz, K. Frommhagen, M. Scholles, M. Schwarzenberg","doi":"10.1109/SIPS.1998.715776","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715776","url":null,"abstract":"A digital imaging device is presented, which allows one-shot acquisition of high-resolution color images. A color depth of 12 bit is provided due to effective noise reduction and pixel correction circuitry. For image compression a wavelet-based algorithm is implemented, which exhibits no visible degradation of image quality at intended compression rates.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115668357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of a nonlinear acoustic echo canceller 非线性回声消除器的设计与实现
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715802
Abdellatif Ben Rabaa, A. Mtibaa, Mohamed Abid, R. Tourki
{"title":"Design and implementation of a nonlinear acoustic echo canceller","authors":"Abdellatif Ben Rabaa, A. Mtibaa, Mohamed Abid, R. Tourki","doi":"10.1109/SIPS.1998.715802","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715802","url":null,"abstract":"An acoustic echo canceller based on neural networks and a fast affine projection (FAP) algorithm is introduced. This structure allows a large set of trade-offs between convergence rate, residual error, tracking capacity, and arithmetic complexity. Hence, the proposed structure has the potential for solving other difficult nonlinear adaptive signal processing tasks such as system identification where nonlinearity and nonstationarity are both important factors. To investigate the feasibility of practical implementation of the proposed structure, a hardware/software implementation is discussed. The specific objective is to find an implementation that satisfies all the system design constraints at least cost.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123162119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and implementation of the Almanet environment Almanet环境的设计和实现
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715813
S. Rumsby, M. Ibrahim, B. Bramer
{"title":"Design and implementation of the Almanet environment","authors":"S. Rumsby, M. Ibrahim, B. Bramer","doi":"10.1109/SIPS.1998.715813","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715813","url":null,"abstract":"Algebraic mapping networks can describe time/space dependencies either at coarse- or fine-grained level. The work reported here is focused on how compiler technology can be adapted to deal with the Almanet description of fine-grain time/space dependencies within a single program. In the first phase, special Almanet statements are embedded in C/C++ and a prototype compiler is developed which successfully interprets these dependencies and generates the correct executables. At the heart of this compiler is the space-time routine which generates a space-time matrix for each dependent variable. The compiler effectively translates an Almanet program, which is basically data-oriented, into separate process-oriented C programs.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digit-serial reconfigurable FPGA logic block architecture 数字串行可重构FPGA逻辑块架构
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715809
H. Lee, G. Sobelman
{"title":"Digit-serial reconfigurable FPGA logic block architecture","authors":"H. Lee, G. Sobelman","doi":"10.1109/SIPS.1998.715809","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715809","url":null,"abstract":"This paper presents a novel field-programmable gate array logic block architecture which incorporates support for digit-serial DSP architectures on a digit-wide basis, without diminishing the support for random and control logic applications. To efficiently realize a digit-serial DSP design on FPGA, one must create an FPGA architecture optimized for those types of systems. The key to the suitability of the FPGA for these applications is the fact that each of its basic blocks is capable of processing a digit size of up to 8 bits. A novel digit-serial FPGA logic block architecture has been proposed to satisfy the requirement of rapid prototyping and efficient implementation of digit-serial DSP applications. Digit-serial DSP designs using the digit-serial FPGA are compared to those implemented on a Xilinx FPGA chip. The results show that the normalized area of digit-serial circuits on the DS-FPGA is only 33/spl sim/54% of the number required on the Xilinx FPGA.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Array signal processing for a wireless MEM sensor network 无线MEM传感器网络的阵列信号处理
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715764
K. Yao, R. E. Hudson, C. Reed, D. Chen, T. Tung, F. Lorenzelli
{"title":"Array signal processing for a wireless MEM sensor network","authors":"K. Yao, R. E. Hudson, C. Reed, D. Chen, T. Tung, F. Lorenzelli","doi":"10.1109/SIPS.1998.715764","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715764","url":null,"abstract":"We first review the high-level signal processing architecture of a wireless MEM sensor system for source detection, signal enhancement, localization, and identification. A blind beamformer using only the measured data of randomly distributed sensors to form a sample correlation matrix is proposed. The maximum power collection criterion is used to obtain array weights from the dominant eigenvector of the sample correlation matrix. An effective blind beamforming estimation of the time delays of the dominant source is demonstrated. Source localization based on a novel least-squares method for time delay estimation is also given. Array system performance based on analysis, simulation, and measured acoustical/seismic sensor data is presented. Applications of such a system to multimedia, intrusion detection, and surveillance are briefly discussed.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Lossless compression of VQ indexes using search-order and correction codes 使用搜索顺序和纠错码的VQ索引无损压缩
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715783
En-Cheng Liu, T.-C. Wang
{"title":"Lossless compression of VQ indexes using search-order and correction codes","authors":"En-Cheng Liu, T.-C. Wang","doi":"10.1109/SIPS.1998.715783","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715783","url":null,"abstract":"In a fixed-rate vector quantization system, an image is divided into smaller blocks, and each block is usually independently encoded by an index of the same length that points to the closest codevector in the codebook. Recently, an algorithm called search-order coding has been proposed to further reduce the bit rate by encoding the indexes but without introducing any extra encoding distortion. We present an improved algorithm that extends the idea of the search-order coding algorithm by encoding the indexes pair by pair. In addition, the correction codes are also adopted to improve the bit rate further. Simulation results indicate that our algorithm is able to achieve a bit rate up to 7% lower than the search-order coding algorithm.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124695301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An overlap-add free musical noise analysis-synthesis system 重叠-添加免费音乐噪声分析-合成系统
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715785
Y. Lam, R. Stewart
{"title":"An overlap-add free musical noise analysis-synthesis system","authors":"Y. Lam, R. Stewart","doi":"10.1109/SIPS.1998.715785","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715785","url":null,"abstract":"An analysis-synthesis system for audio signals using sinusoidal model-based algorithms for harmonic component reconstruction and noise modeling for stochastic component synthesis has recently demonstrated the generation of high-quality synthetic signals. However current approaches, which mainly use phase randomization noise-driven source filter models with overlap-add techniques, have degraded the performance for signals consisting of highly time-localized events such as transients. First, the undesirable effects of window overlap-add analysis-synthesis on non-stationary signals are addressed, second, an overlap-add-free analysis-synthesis system is proposed based on a coherent loss compensation concept, and third, a noise synthesis model based on the perceptual mechanism is described using sinusoidal components randomly spaced in the frequency domain and novel phase prediction and phase correction techniques. The listening results illustrate our overlap-add free noise synthesis model has better performance than the conventional window overlap-add noise-driven filter models with phase randomization for highly time-localized signals.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116207613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital demodulator matching on a FPGA FPGA上的数字解调器匹配
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715799
E. Boutillon, J. Danger, Leila Maria Garcia Fonseca, A. Garcia, L. González
{"title":"Digital demodulator matching on a FPGA","authors":"E. Boutillon, J. Danger, Leila Maria Garcia Fonseca, A. Garcia, L. González","doi":"10.1109/SIPS.1998.715799","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715799","url":null,"abstract":"We present a digital demodulator based on a FPGA design. After the presentation of the demodulator algorithm, we describe its integration on a programmable logic device (ALTERA FLEX10K100). We focus on how the FPGA characteristics can change the expertise of the designer at all levels of the design flow, from bit level to algorithm level and methodology level.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126264481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput 基于SAFER K-128算法的可重用加密VLSI核，吞吐量为251.8 Mbit/s
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715806
A. Schubert, V. Meyer, W. Anheier
{"title":"Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput","authors":"A. Schubert, V. Meyer, W. Anheier","doi":"10.1109/SIPS.1998.715806","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715806","url":null,"abstract":"A VLSI implementation of the symmetric block cipher SAFER K-128 (Secure And Fast Encryption Routine with a Key length of 128 bits) is presented. Possibilities for optimization of the VLSI architecture are explained. The optimizations are based on algorithm-specific properties and lead to considerable hardware reduction. The result is a reusable cryptographic VLSI core that allows a data throughput of 251.8 Mbit/s at a clock frequency of 40 MHz in a 0.7 /spl mu/m CMOS process. Therefore, the circuit is usable in integrated systems for high-speed data encryption.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130002733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Partitioning analog and digital processing in a single-chip GPS receiver 在单片GPS接收机中划分模拟和数字处理
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715788
S. Reader, W. Namgoong, T. Meng
{"title":"Partitioning analog and digital processing in a single-chip GPS receiver","authors":"S. Reader, W. Namgoong, T. Meng","doi":"10.1109/SIPS.1998.715788","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715788","url":null,"abstract":"In the near future, Global Positioning System (GPS) data will be used in a wide variety of portable, mobile electronic devices. Shrinking feature sizes, combined with the need for low-power, lightweight components, will drive an entire GPS receiver onto a single, mixed-signal die. A major design issue in mixed-signal systems is the effect of digital switching noise coupled to sensitive analog circuits through the substrate. A method is proposed for minimizing this effect by partitioning digital and analog processing into separate time blocks. The resulting trade-off between lost signal and increased energy consumption is explored. In particular, a GPS synchronizer design is analyzed with respect to modifications that can be made to increase performance, while minimizing any associated energy penalty.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127027590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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