Reusable cryptographic VLSI core based on the SAFER K-128 algorithm with 251.8 Mbit/s throughput

Abstract

A VLSI implementation of the symmetric block cipher SAFER K-128 (Secure And Fast Encryption Routine with a Key length of 128 bits) is presented. Possibilities for optimization of the VLSI architecture are explained. The optimizations are based on algorithm-specific properties and lead to considerable hardware reduction. The result is a reusable cryptographic VLSI core that allows a data throughput of 251.8 Mbit/s at a clock frequency of 40 MHz in a 0.7 /spl mu/m CMOS process. Therefore, the circuit is usable in integrated systems for high-speed data encryption.