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1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)最新文献

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Compactly merged arithmetic for wavelet transforms 小波变换的紧合并算法
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715810
Gwangwoo Choe, E. Swartzlander
{"title":"Compactly merged arithmetic for wavelet transforms","authors":"Gwangwoo Choe, E. Swartzlander","doi":"10.1109/SIPS.1998.715810","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715810","url":null,"abstract":"A new form of merged arithmetic is presented to compute wavelet transforms for image compression. Our approach is suitable for a wavelet-specific processor, which offers high-performance for image compression with wavelet transforms. This arithmetic is a compact form of merged arithmetic that is specifically optimized for the wavelet transform by eliminating bit-products, thus reducing the size of reduction. It develops a dual merging process to segregate the positive filter coefficients from the negative ones. Furthermore, it utilizes the bitmaps of the filter coefficients, fixed for a specific wavelet filter, and offers superior performance in both speed and size. Employing pipeline techniques, this approach provides an attractive circuit for the wavelet method of image compression.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123131153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel 四类PRML信道的高性能自适应均衡器和维特比解码器的快速设计
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715793
B.D.E. Smith, J. McCanny
{"title":"Rapid design of high performance adaptive equalizer and Viterbi decoder for the class-IV PRML channel","authors":"B.D.E. Smith, J. McCanny","doi":"10.1109/SIPS.1998.715793","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715793","url":null,"abstract":"This paper describes methods for the rapid design and VLSI implementation of two key components (the adaptive filter and Viterbi decoder) of the class-IV partial response maximum likelihood channel (PR-IV). These are implemented using parameterized modules, constructed from a synthesizable silicon architecture library containing core DSP and arithmetic functions. Design studies, based on a 0.35 micron 3.3 V standard cell CMOS process, indicate that worst case sampling rates of 180 mega-samples per second are achievable with a power consumption of 0.8 W and an area of 4.3 mm/sup 2/. Higher sampling rates can be obtained by operating a number of filter modules in parallel. This approach offers power saving advantages when compared with systems employing pipelined filters operating at the same speed.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133205870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Protecting ownership rights of a lossless image coder through hierarchical watermarking 通过分层水印保护无损图像编码器的所有权
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715770
H. Kim, W. Mangione-Smith, M. Potkonjak
{"title":"Protecting ownership rights of a lossless image coder through hierarchical watermarking","authors":"H. Kim, W. Mangione-Smith, M. Potkonjak","doi":"10.1109/SIPS.1998.715770","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715770","url":null,"abstract":"Current market forces make it necessary for designers to protect their work against illicit use. Digital watermarks can be used to sign a design and thus establish ownership. We present a hierarchical set of techniques for intellectual property protection of a linear predictive image coder. Watermarking techniques employed include switching entries in the Huffman coding table, applying zero cost hardware transformations, embedding a signature in the scheduling of shared hardware resources, and applying a watermark to the physical layout. Using these methods, it is possible to watermark complete ASIC or FPGA designs with little overhead in performance or achieved compression rates.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114674098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Rapid design of a single chip adaptive beamformer 单片自适应波束形成器的快速设计
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715791
G. Lightbody, R. Woods, J. McCanny, R. Walke, Y. Hu, D. Trainor
{"title":"Rapid design of a single chip adaptive beamformer","authors":"G. Lightbody, R. Woods, J. McCanny, R. Walke, Y. Hu, D. Trainor","doi":"10.1109/SIPS.1998.715791","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715791","url":null,"abstract":"This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 gigaflops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125565901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low-complexity VLSI design and implementation of FFT-based multi-carrier direct sequence spread spectrum transceiver 基于fft的多载波直接序列扩频收发器的低复杂度VLSI设计与实现
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715796
S. Hong, J. Yi, W. Stark
{"title":"Low-complexity VLSI design and implementation of FFT-based multi-carrier direct sequence spread spectrum transceiver","authors":"S. Hong, J. Yi, W. Stark","doi":"10.1109/SIPS.1998.715796","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715796","url":null,"abstract":"A design and implementation of an all-digital VLSI multi-carrier direct-sequence spread-spectrum IF/baseband transceiver architecture is presented. The paper describes a low-complexity VLSI architecture incorporating the fast Fourier transform for multi-carrier modulation and demodulation. The architecture supports variable data rate and variable quality of service (QoS) transmission where both rate and reliability are controlled by the length of pseudo-random noise spreading sequence. Nyquist windowing is utilized to reduce the sensitivity to spurious sine waves and to frequency deviations in the receiver. A two-dimensional simple sliding correlation technique is incorporated for efficient data frame and spreading sequence synchronization. The architecture is capable of handling various data rates up to 1.024 Mbit/s through 64 equally spaced carrier frequencies covering 65.536 MHz bandwidth. The entire transceiver is implemented with 0.6-/spl mu/m CMOS technology standard cells.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A study of loop unrolling for VLIW-based DSP processors 基于vliw的DSP处理器的循环展开研究
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715814
S. Sair, D. Kaeli, W. Meleis
{"title":"A study of loop unrolling for VLIW-based DSP processors","authors":"S. Sair, D. Kaeli, W. Meleis","doi":"10.1109/SIPS.1998.715814","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715814","url":null,"abstract":"With the growing popularity of DSP and their associated applications, cost-effective software development has become a major issue. High-level language compilers are becoming more commonplace in the DSP world. While these compilers can generate correct code for DSP architectures, there remains considerable room for performance improvements. This paper addresses issues related to DSP compilation, focusing specifically on unrolling techniques proposed for VLIW-based DSP architectures.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127970344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Self-regulated GPS navigation processor 自调节GPS导航处理器
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715795
H.-W. Lee, T. Meng
{"title":"Self-regulated GPS navigation processor","authors":"H.-W. Lee, T. Meng","doi":"10.1109/SIPS.1998.715795","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715795","url":null,"abstract":"We implement a navigation processor for the stand-alone global positioning system (GPS). We develop a behavior observer to monitor user dynamics and to aid a Kalman filter performing continuous position and speed estimates. The behavior observer consists of a fast observer and a signal detector. The fast observer tracks user maneuvers. The signal detector compares outputs of the fast observer and the Kalman filter to determine user dynamics and corrects operations of the Kalman filter. Simulations using fixed-point arithmetic demonstrate that dramatic improvements on tracking ability can be achieved without degradation in steady-state position accuracy.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Arbitration schemes synthesis approach for multiprocessor systems 多处理机系统的仲裁方案综合方法
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715812
A. Zitouni, Mohamed Abid, R. Tourki
{"title":"Arbitration schemes synthesis approach for multiprocessor systems","authors":"A. Zitouni, Mohamed Abid, R. Tourki","doi":"10.1109/SIPS.1998.715812","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715812","url":null,"abstract":"The aim of this paper is to present an arbiter synthesis approach stated as an arbitration scheme generation/selection problem. This approach may be easily inserted in an extendible system co-design methodology. It assumes that many co-design tasks have been performed, and it aims to automate the resolution of the access conflict problem that may be inevitably encountered whenever there is a resource contention in the system. The proposed approach allows us to transform a system composed of high-level processes that share the same channels and the same variables in a disordered manner into a set of processes executed by interconnected processors and hardware devices (e.g., ASIC, FPGA, etc.) that share the same resources such as memories and buses using the most efficient arbitration scheme. This approach is basically based on an algorithm that allows respectively the automatic generation/selection of the arbitration scheme, and the fixed priority assignment in a manner that minimizes the real-time cost.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122886851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scheduling strategies for low-energy programmable digit-serial Reed-Solomon codecs 低能耗可编程数字串行Reed-Solomon编解码器的调度策略
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715790
L. Song, K. K. Parhi
{"title":"Scheduling strategies for low-energy programmable digit-serial Reed-Solomon codecs","authors":"L. Song, K. K. Parhi","doi":"10.1109/SIPS.1998.715790","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715790","url":null,"abstract":"This paper considers two types of digit-serial finite field multiplications, and their applications to the design of low-energy high-performance Reed-Solomon codecs in software, based on a digit-serial finite field data path architecture. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. It is shown that for larger digit-sizes, more than 60% energy reduction and more than one-third energy-delay reduction can be achieved be using these scheduling approaches for the digit-serial data path as compared with that for the parallel data path, for 2-error-correcting Reed-Solomon(n,k) codecs over GF(2/sup 8/), where n can range from 5 to 255. When area becomes a critical design constraint, smaller digit-sizes must be used. In that case, the energy and energy-delay reduction can be achieved using combined scheduling strategies.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114150528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Real-time software video encoder on a multimedia RISC processor 基于多媒体RISC处理器的实时软件视频编码器
1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI: 10.1109/SIPS.1998.715766
T. Miyazaki, I. Kuroda
{"title":"Real-time software video encoder on a multimedia RISC processor","authors":"T. Miyazaki, I. Kuroda","doi":"10.1109/SIPS.1998.715766","DOIUrl":"https://doi.org/10.1109/SIPS.1998.715766","url":null,"abstract":"A real-time software MPEG1 video encoder on a multimedia RISC processor, V830R/AV, is presented. The V830R/AV processor provides 64-bit SIMD media-enhanced instructions. The motion estimation is accelerated by a combination of the partial absolute difference instruction and a method to sum up partial block differences. The IDCT in conformity with the IEEE standard is simply implemented by the multiply-accumulate instruction with symmetric rounding. The encoder program structure is carefully reconstructed to reduce instruction cache misses, which heavily degrade the processor performance. Preload instructions are used to load data to the data cache in parallel with successive instruction execution. Consequently, the cache miss penalties are drastically reduced. The current version of the software MPEG1 video encoder on the 200 MHz V830R/AV processor encodes SIF (352/spl times/240 pels) video at 30 frames/s with I, P and B picture types in 193 M clocks/s.","PeriodicalId":151031,"journal":{"name":"1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121792392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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